diff mbox series

[3/7] drm/amd/display: Add new blob properties for secure display CRC

Message ID 20230516053931.1700117-4-HaoPing.Liu@amd.com (mailing list archive)
State New, archived
Headers show
Series Secure display with new CRTC properties | expand

Commit Message

Liu, HaoPing (Alan) May 16, 2023, 5:39 a.m. UTC
Add a new blob properties and implement the property creation and
attachment functions for the CRC result values of secure display.

Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  3 +++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |  1 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 10 ++++++++
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    | 23 ++++++++++++++++---
 include/uapi/drm/drm_mode.h                   | 19 +++++++++++++++
 5 files changed, 53 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ee57c659f230..74e42257a608 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -503,6 +503,9 @@  struct amdgpu_display_manager {
 
 	/* properties for secure_display ROI configuration */
 	struct drm_property *secure_display_roi_property;
+
+	/* properties for secure_display CRC information */
+	struct drm_property *secure_display_crc_property;
 #endif
 	/**
 	 * @hpd_rx_offload_wq:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index e7259ec1d644..a83cabb9b1a6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -550,6 +550,7 @@  amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
 		DRM_ERROR("amdgpu: failed to create secure display properties.\n");
 
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
+		spin_lock_init(&secure_display_ctxs[i].crc.lock);
 		INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);
 		INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
 		secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
index 66f29e3de9f9..f2def8c20d83 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
@@ -40,6 +40,14 @@  enum amdgpu_dm_pipe_crc_source {
 };
 
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
+struct crc_data {
+	uint32_t crc_R;
+	uint32_t crc_G;
+	uint32_t crc_B;
+	uint32_t frame_count;
+	spinlock_t lock;
+};
+
 struct crc_window_param {
 	uint16_t x_start;
 	uint16_t y_start;
@@ -64,6 +72,8 @@  struct secure_display_context {
 
 	/* Region of Interest (ROI) */
 	struct rect rect;
+
+	struct crc_data crc;
 };
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index e1a17f2d6f2d..4457eac8273e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -299,16 +299,30 @@  int amdgpu_dm_crtc_create_secure_display_properties(struct amdgpu_device *adev)
 {
 	struct amdgpu_display_manager *dm = &adev->dm;
 	struct drm_device *dev = adev_to_drm(adev);
-	struct drm_property *roi_prop;
+	struct drm_property *roi_prop, *crc_prop;
 
 	roi_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
 					"SECURE_DISPLAY_ROI", 0);
-	if (!roi_prop)
-		return -ENOMEM;
+
+	crc_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+					"SECURE_DISPLAY_CRC", 0);
+
+	if (!roi_prop || !crc_prop)
+		goto fail;
 
 	dm->secure_display_roi_property = roi_prop;
+	dm->secure_display_crc_property = crc_prop;
 
 	return 0;
+
+fail:
+	if (roi_prop)
+		drm_property_destroy(dev, roi_prop);
+
+	if (crc_prop)
+		drm_property_destroy(dev, roi_prop);
+
+	return -ENOMEM;
 }
 
 void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev,
@@ -318,6 +332,9 @@  void amdgpu_dm_crtc_attach_secure_display_properties(struct amdgpu_device *adev,
 
 	if (dm->secure_display_roi_property)
 		drm_object_attach_property(&crtc->base, dm->secure_display_roi_property, 0);
+
+	if (dm->secure_display_crc_property)
+		drm_object_attach_property(&crtc->base, dm->secure_display_crc_property, 0);
 }
 
 static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 98e0a0aaa1c3..8c488ce59e7a 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -1323,6 +1323,25 @@  struct drm_roi {
 	__u8 pad[7];
 };
 
+/**
+ * struct drm_crc - The CRC value of the corresponding ROI of secure display.
+ * @crc_r: CRC value of red color.
+ * @crc_g: CRC value of green color.
+ * @crc_b: CRC value of blue color.
+ * @frame_count: a referenced frame count to indicate which frame the CRC values
+ *  are generated at.
+ *
+ * Userspace uses this structure to retrieve the CRC value of the current ROI of
+ * secure display. @frame_count will be reset once a new ROI is updated or it reaches
+ * its maximum value.
+ */
+struct drm_crc {
+	__u32 crc_r;
+	__u32 crc_g;
+	__u32 crc_b;
+	__u32 frame_count;
+};
+
 #if defined(__cplusplus)
 }
 #endif