@@ -8864,7 +8864,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
(struct drm_roi *)dm_new_crtc_state->secure_display_state.roi_blob->data;
if (roi_data->secure_display_enable) {
+ struct secure_display_context *secure_display_ctx =
+ &dm->secure_display_ctxs[acrtc->crtc_id];
+
if (!amdgpu_dm_crc_window_is_activated(crtc)) {
+ init_completion(&secure_display_ctx->crc.completion);
+
/* Enable secure display: set crc source to "crtc" */
amdgpu_dm_crtc_set_secure_display_crc_source(crtc, "crtc");
@@ -8874,7 +8879,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
acrtc->dm_irq_params.window_param.activated = true;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
- }
+ } else
+ reinit_completion(&secure_display_ctx->crc.completion);
/* Update ROI: copy ROI from dm_crtc_state to dm_irq_params */
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
@@ -619,6 +619,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
secure_display_ctx->crc.crc_R = crc[0];
secure_display_ctx->crc.crc_G = crc[1];
secure_display_ctx->crc.crc_B = crc[2];
+ complete_all(&secure_display_ctx->crc.completion);
}
spin_unlock_irqrestore(&secure_display_ctx->crc.lock, flags1);
@@ -46,6 +46,7 @@ struct crc_data {
uint32_t crc_B;
uint32_t frame_count;
spinlock_t lock;
+ struct completion completion;
};
struct crc_window_param {
@@ -380,6 +380,10 @@ static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
struct secure_display_context *secure_display_ctx =
&adev->dm.secure_display_ctxs[crtc->index];
+ if (amdgpu_dm_crc_window_is_activated(crtc))
+ wait_for_completion_interruptible_timeout(
+ &secure_display_ctx->crc.completion, 10 * HZ);
+
if (property == adev->dm.secure_display_roi_property)
*val = (dm_state->secure_display_state.roi_blob)
? dm_state->secure_display_state.roi_blob->base.id : 0;
When the user requests for secure display ROI or CRC data, the request will be blocked until the CRC result of current frame is calculated and updated to secure display ctx in vline0 irq handler. Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ++++ 4 files changed, 13 insertions(+), 1 deletion(-)