From patchwork Sat Jun 24 00:41:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A69F6C001B0 for ; Sat, 24 Jun 2023 00:41:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECD5910E6EA; Sat, 24 Jun 2023 00:41:12 +0000 (UTC) Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [5.144.164.168]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1C5B10E087; Sat, 24 Jun 2023 00:41:05 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 57A103F7AB; Sat, 24 Jun 2023 02:41:03 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:00 +0200 Subject: [PATCH 02/15] dt-bindings: clock: qcom,dispcc-sm6125: Remove unused GCC_DISP_AHB_CLK MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-2-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The downsteam driver for dispcc only ever gets and puts this clock without ever using it in the clocktree; this unnecessary workaround was never ported to mainline, hence the driver doesn't consume this clock and shouldn't be required by the bindings. Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings") Signed-off-by: Marijn Suijten Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 8a210c4c5f82..2acf487d8a2f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -28,7 +28,6 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY - - description: AHB config clock from GCC clock-names: items: @@ -38,7 +37,6 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - - const: cfg_ahb_clk '#clock-cells': const: 1 @@ -71,15 +69,13 @@ examples: <&dsi0_phy 1>, <&dsi1_phy 1>, <&dp_phy 0>, - <&dp_phy 1>, - <&gcc GCC_DISP_AHB_CLK>; + <&dp_phy 1>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk", - "cfg_ahb_clk"; + "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #power-domain-cells = <1>; };