| Message ID | 20230713103346.1163315-9-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSC misc fixes | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ankit > Nautiyal > Sent: Thursday, July 13, 2023 4:04 PM > To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for > printing DSC info > > DSC compressed bpp and slice counts are already getting printed at the end > of dsc compute config. Remove extra logs. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > drivers/gpu/drm/i915/display/intel_dp.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index c1fd448d80e1..23ede846202c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp > *intel_dp, > output_bpp); > } > pipe_config->dsc.slice_count = dsc_dp_slice_count; > - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d > slice count %d\n", > - pipe_config->dsc.compressed_bpp, > - pipe_config->dsc.slice_count); > } > /* > * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate > -- > 2.40.1
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c1fd448d80e1..23ede846202c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); } /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-)