Message ID | 20230721165328.3968759-2-l.stach@pengutronix.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2,1/2] drm/bridge: tc358767: increase PLL lock time delay | expand |
On 7/21/23 18:53, Lucas Stach wrote: > From: David Jander <david@protonic.nl> > > The documentation is not clear about how this delay works. > Empirical tests have shown that with a VSDELAY of 0, the first > scanline is not properly formatted in the output stream when > DSI->DP mode is used. The calculation spreadsheets from Toshiba > seem to always make this value equal to the HFP + 10 for DSI->DP > use-case. For DSI->DPI this value should be > 2 and for DPI->DP > it seems to always be 0x64. > > Signed-off-by: David Jander <david@protonic.nl> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> # TC9595 > Reviewed-by: Marek Vasut <marex@denx.de> Applied both to drm-misc-next , thanks !
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 29721e26de5d..5c33f13fdb39 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -817,7 +817,7 @@ static int tc_set_common_video_mode(struct tc_data *tc, * sync signals */ ret = regmap_write(tc->regmap, VPCTRL0, - FIELD_PREP(VSDELAY, 0) | + FIELD_PREP(VSDELAY, right_margin + 10) | OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); if (ret) return ret;