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Mon, 7 Aug 2023 05:22:31 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 6/9] drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP Date: Mon, 7 Aug 2023 13:26:05 +0800 Message-Id: <20230807052608.3038698-7-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230807052608.3038698-1-victor.liu@nxp.com> References: <20230807052608.3038698-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR01CA0006.apcprd01.prod.exchangelabs.com (2603:1096:4:191::14) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|PA4PR04MB9390:EE_ X-MS-Office365-Filtering-Correlation-Id: 60175840-690e-4e27-07eb-08db97064c3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hsKnxtTha/wnLGFbbqijg60wb40XGLWtM0p6PQDc8AsF4f4l/ncxFPyab4mBDn9i4vTG70sr7OLv0cIcUjKMxR0SRa5zHhBubF7SzU/yCz3BHZclnAgC0dY/2CFSRpMOOxTJ+MR12GuUwO++z17U57nsVjukgpRvYuRRE/i4zbBvU8XyH0l0k2/ZEuAmWgy8eO9wEPGokSUXK/Jj+4Ze1zwrrqzOKOk/Ns+u8GgW7PbIBhdaV4ogG5On+eoEPcehp7YQGse6ReNb/sw2OMwP4wfVqMB7gy+syQWMIxb73uuiNoaJhraHVkAkQKXYPJwXPU1azCcO6KgRK+tjTUlhIWN40ssG3C/XSolmOFgmVzrOUYFgDCLgCoAnEdsWJg3i7OG1+WQi/Ocuo10xX+6SVlDThN3dR1DD/hVNDjmp4Qp2okGuCIQWkNnmH5s1fh6vZvQkc1ArW1Z9b6AXQmRUXsOls3FyG104ORGv89XGQdk/6J9/NKP9ZWgMIMNVCEKT2nYWL8czYjxlJI1LVCXWwfc0TbxuMuSKOH2LrV5EkY31J88qMTvLHvXR4GR6igTm/AJ8ghtjKovHjDdcMFBSrStdjOzZFLpkF5LbkzyHkytHAZfEhGSud0CMuZpeQg+5 X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Hence, the below table comes in. +------------+----------+-------+ | data lanes | min lbcc | bytes | +------------+----------+-------+ | 1 | 10 | 1*10 | +------------+----------+-------+ | 2 | 5 | 2*5 | +------------+----------+-------+ | 3 | 4 | 3*4 | +------------+----------+-------+ | 4 | 3 | 4*3 | +------------+----------+-------+ Implement the minimum lbcc numbers to make sure that the values programmed into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum number requirement. For DSI_VID_HLINE_TIME register, it seems that the value programmed should be based on mode->htotal as-is, instead of sum up HSA, HBP, HFP and HDISPLAY. This helps the case where Raydium RM67191 DSI panel is connected, since it's video timing for hsync length is only 2 pixels and without this patch the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes. Signed-off-by: Liu Ying Reviewed-by: Neil Armstrong --- v2->v3: * Add Neil's R-b tag from v1. v1->v2: * No change. drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 332388fd86da..536306ccea5a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -757,12 +757,19 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); } +static const u32 minimum_lbccs[] = {10, 5, 4, 3}; + +static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi) +{ + return minimum_lbccs[dsi->lanes - 1]; +} + /* Get lane byte clock cycles. */ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, const struct drm_display_mode *mode, u32 hcomponent) { - u32 frac, lbcc; + u32 frac, lbcc, minimum_lbcc; int bpp; bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); @@ -778,6 +785,11 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, if (frac) lbcc++; + minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi); + + if (lbcc < minimum_lbcc) + lbcc = minimum_lbcc; + return lbcc; }