From patchwork Wed Aug 16 11:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13355048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00866C001E0 for ; Wed, 16 Aug 2023 11:26:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2928F10E355; Wed, 16 Aug 2023 11:25:58 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FAD910E34A for ; Wed, 16 Aug 2023 11:25:51 +0000 (UTC) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 70E621B83; Wed, 16 Aug 2023 13:24:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692185077; bh=TUkJXEdGx2L3x9eOO5C14gMRZFfjPUo5XB/iG7hSXNo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=wT8uai6kYpCT7e997tqiHmEJ/tk3gv0JlMksq2mqAvavq+vOILPJrOjwZlo1evyT4 dLqiG035pa5IgCTPz09hF0mrnNPpUuhGZCStlA8A1VXh3lne83cXa/XLf7k8zIXglm eLWPlg1bbdyZkXTKfJcfoxEWUMe1bxxy1QYmnmb4= From: Tomi Valkeinen Date: Wed, 16 Aug 2023 14:25:07 +0300 Subject: [PATCH v2 04/12] drm/bridge: tc358768: Cleanup PLL calculations MIME-Version: 1.0 Message-Id: <20230816-tc358768-v2-4-242b9d5f703a@ideasonboard.com> References: <20230816-tc358768-v2-0-242b9d5f703a@ideasonboard.com> In-Reply-To: <20230816-tc358768-v2-0-242b9d5f703a@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2487; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=TUkJXEdGx2L3x9eOO5C14gMRZFfjPUo5XB/iG7hSXNo=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk3LI1SArTyutIV17XojzHHC5KuLY3z8/2Bvl6T W9ACZ1vZH6JAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZNyyNQAKCRD6PaqMvJYe 9XjrD/45qk5Y/wFlKk/Bcmd+Exi9hMi7jS30ahdF3g95qpQPuUJxJZ1xRhvuB4U5nNqXmQEb04Q 6adABiSq1H0UhTkvKRghu3IQvlyE4KIDgTjLNF+sQVERbtx9I1eUg0sob89lwHzdId8fdvc7+dU kxx3GHiq+LkAhqRmaZKYL2ORkUs04iSyKIMThQUeFHMMsNEqgm62YKfWkMSG8nzP1c9xW+Hjjmg NpXP9HK+cRwV5oB8xL/RmZ5dM/+vf/Iu4oVgIYFDqa61Atk8bsHxsnPWChvKRCLBgcfCojeO2xj PtXwixAYpKRcVqeETBN81igYzw5y+1sKCzR2+F6ZVlch3uN71tolfGX45wsM9Va9wgdas2ubS7u joIT/iwSmSqYnSgixAGNw00FmZyJS9KMnxGBJyh3BUPmVOBz1Q8qIYVBXavTqvq5eeB2Zn3E/Cq 3YkY+4a9X22Q1NE+sU2vwtqVcPD212UcnaYszOqIJlRgvRYSnYoZxR0egWlHW+J1NEkjcwgeLDh vBX3afulH4ueTLOygHdy+ObyjSvvGRGSsPQmoPQOwqR2yAufCJhznuX8CHdY5VKboRwOgdZKgou ItYPjwUiM6A7zy/FZz5w62KpJPNGjpmSzkkmal1o/QTMsHjgSqEexVTwPzqiz0YtXcE1B+vUE2t pX8N+4LYn/GBZ5g== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Aradhya Bhatia Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" As is quite common, some of TC358768's PLL register fields are to be programmed with (value - 1). Specifically, the FBD and PRD, multiplier and divider, are such fields. However, what the driver currently does is that it considers that the formula used for PLL rate calculation is: RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] where FBD and PRD are values directly from the registers, while a more sensible way to look at it is: RefClk * FBD / PRD * (1 / (2^FRS)) and when the FBD and PRD values are written to the registers, they will be subtracted by one. Change the driver accordingly, as it simplifies the PLL code. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index b668f77673c3..d5831a1236e9 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -316,7 +316,7 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); - /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ + /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ for (i = 0; i < ARRAY_SIZE(frs_limits); i++) if (target_pll >= frs_limits[i]) @@ -336,19 +336,19 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, best_prd = 0; best_fbd = 0; - for (prd = 0; prd < 16; ++prd) { - u32 divisor = (prd + 1) * (1 << frs); + for (prd = 1; prd <= 16; ++prd) { + u32 divisor = prd * (1 << frs); u32 fbd; - for (fbd = 0; fbd < 512; ++fbd) { + for (fbd = 1; fbd <= 512; ++fbd) { u32 pll, diff, pll_in; - pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); + pll = (u32)div_u64((u64)refclk * fbd, divisor); if (pll >= max_pll || pll < min_pll) continue; - pll_in = (u32)div_u64((u64)refclk, prd + 1); + pll_in = (u32)div_u64((u64)refclk, prd); if (pll_in < 4000000) continue; @@ -611,7 +611,7 @@ static int tc358768_setup_pll(struct tc358768_priv *priv, mode->clock * 1000); /* PRD[15:12] FBD[8:0] */ - tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); + tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ tc358768_write(priv, TC358768_PLLCTL1,