| Message ID | 20230825-pll-mipi_keep_rate-v1-2-35bc43570730@oltmanns.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Make Allwinner A64's pll-mipi keep its rate when parent rate changes | expand |
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 8951ffc14ff5..d22094ce1d66 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -180,7 +180,8 @@ static struct ccu_nkm pll_mipi_clk = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", &ccu_nkm_ops, - CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT), + CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT | + CLK_KEEP_RATE), .features = CCU_FEATURE_CLOSEST_RATE, }, };
Keep the clock rate of Allwinner A64's pll-mipi even when the parent (pll-video0) changes its rate. This is required, to drive both an LCD and HDMI display, because both have pll-video0 as an ancestor. Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)