diff mbox series

[RFC,18/33] drm/i915/color: Add HDR plane LUT range data to color pipeline

Message ID 20230829160422.1251087-19-uma.shankar@intel.com (mailing list archive)
State New, archived
Headers show
Series Add Support for Plane Color Pipeline | expand

Commit Message

Shankar, Uma Aug. 29, 2023, 4:04 p.m. UTC 
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Create a helper function to add details about LUT ranges that HDR
planes can support. Userspace can parse through this information
to generate proper LUT data for respective hardware blocks. It will
be exposed to the user space by the color pipeline.

Co-developed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 09e50659befd..99ae3f4fca05 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -28,6 +28,7 @@ 
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsb.h"
+#include "skl_universal_plane.h"
 
 struct intel_color_funcs {
 	int (*color_check)(struct intel_crtc_state *crtc_state);
@@ -3976,6 +3977,52 @@  struct drm_color_op color_pipeline_hdr[] = {
 	},
 };
 
+__maybe_unused
+static int intel_prepare_plane_color_pipeline(struct drm_plane *plane)
+{
+	struct drm_i915_private *i915 = to_i915(plane->dev);
+	struct drm_property_blob *blob[2] = {NULL};
+	int ret = 0, i = 0;
+
+	if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) {
+		blob[i] = drm_property_create_blob(plane->dev,
+						   sizeof(xelpd_pre_csc_hdr),
+						   xelpd_pre_csc_hdr);
+		if (IS_ERR(blob[i])) {
+			ret = PTR_ERR(blob[i]);
+			goto out;
+		}
+
+		/*
+		 * In HDR color pipeline PRE-CSC and POST-CSC are positioned
+		 * at 0th and 2nd index/position
+		 */
+		color_pipeline_hdr[0].blob_id =
+			blob[i++]->base.id;
+
+		blob[i] = drm_property_create_blob(plane->dev,
+						   sizeof(xelpd_post_csc_hdr),
+						   xelpd_post_csc_hdr);
+		if (IS_ERR(blob[i])) {
+			ret = PTR_ERR(blob[i]);
+			goto out;
+		}
+
+		color_pipeline_hdr[2].blob_id =
+			blob[i++]->base.id;
+	}
+
+out:
+	if (ret) {
+		for (int j = 0; j < i; j++) {
+			if (blob[j])
+				drm_property_blob_put(blob[j]);
+		}
+	}
+
+	return ret;
+};
+
 void intel_color_crtc_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);