diff mbox series

[RFC,19/33] drm/i915/color: Add SDR plane LUT range data to color pipeline

Message ID 20230829160422.1251087-20-uma.shankar@intel.com (mailing list archive)
State New, archived
Headers show
Series Add Support for Plane Color Pipeline | expand

Commit Message

Shankar, Uma Aug. 29, 2023, 4:04 p.m. UTC 
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add LUT ranges for color blocks in SDR planes. Userspace can
parse through this information to generate proper LUT data for
respective hardware blocks. It will be exposed to the user space
by the color pipeline.

Co-developed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 99ae3f4fca05..a8c6be70c859 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4010,6 +4010,22 @@  static int intel_prepare_plane_color_pipeline(struct drm_plane *plane)
 
 		color_pipeline_hdr[2].blob_id =
 			blob[i++]->base.id;
+	} else {
+		blob[i] = drm_property_create_blob(plane->dev,
+						   sizeof(xelpd_pre_post_csc_sdr),
+						   xelpd_pre_post_csc_sdr);
+		if (IS_ERR(blob[i])) {
+			ret =  PTR_ERR(blob[i]);
+			goto out;
+		}
+
+		/*
+		 * In SDR color pipeline PRE-CSC and POST-CSC blocks are positioned
+		 * at 0th and 1st index/postion.
+		 * LUT ranges for SDR planes are similar for pre and post-csc blocks
+		 */
+		color_pipeline_sdr[0].blob_id =
+			color_pipeline_sdr[1].blob_id = blob[i++]->base.id;
 	}
 
 out: