Message ID | 20231018035212.1778767-1-victor.liu@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode | expand |
On Wed, 18 Oct 2023 11:52:12 +0800, Liu Ying wrote: > In order to support burst mode, vendor drivers set lane_mbps higher than > bandwidth through DPI interface. So, calculate horizontal component lane > byte clock cycle(lbcc) based on lane_mbps instead of pixel clock rate for > burst mode. > > Applied, thanks! [1/1] drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode commit: 93e82bb4de0196c4caeca1d8a6eef67863981d8f Best regards,
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 8789eca26188..824fb3c65742 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -774,13 +774,19 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, u32 frac, lbcc, minimum_lbcc; int bpp; - bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - if (bpp < 0) { - dev_err(dsi->dev, "failed to get bpp\n"); - return 0; - } + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + /* lbcc based on lane_mbps */ + lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; + } else { + /* lbcc based on pixel clock rate */ + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + if (bpp < 0) { + dev_err(dsi->dev, "failed to get bpp\n"); + return 0; + } - lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8); + lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8); + } frac = lbcc % mode->clock; lbcc = lbcc / mode->clock;