From patchwork Tue Oct 24 05:50:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislaw Gruszka X-Patchwork-Id: 13433914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61ABEC00A8F for ; Tue, 24 Oct 2023 05:50:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 787AB10E2A8; Tue, 24 Oct 2023 05:50:44 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6141910E008 for ; Tue, 24 Oct 2023 05:50:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698126642; x=1729662642; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=JWTEjA2M8Jh2V2QG1O1XppL4VQrqYOlkO7ZRdyv7P9c=; b=YmsLsyVl2BpK43MuD//wwR3mVHykp3TlSQOv7Wpoq1jXx+mnKOflvOQW 4nUpON/VVMnNCsropywysv62UzLe6ci0r3PDIrNlFGJ7IFdwAyJUvi9JY qvEMCSKR5texCR+oomufFPtrQsh4Ii4Jn5iQ+VHzfoqDJfMtIy+BVOr3U o7m1iNUOcYNwdMEbxKhiMYQoNdcrZpeCK6ygJhjyEvMdq3MZ8QLGgYkVg Fc/1SgUq0Yu00NtZjr0iL8lf0fVHP+fNkdoXVbIPZd1ZC+Mg0lqPCqMuj TWp0zvkXUO0lMEFw8NKz97zIfofF6fhptABT1i1WhXNsfH8UhM+uYGUOk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="384188496" X-IronPort-AV: E=Sophos;i="6.03,246,1694761200"; d="scan'208";a="384188496" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 22:50:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="902053918" X-IronPort-AV: E=Sophos;i="6.03,246,1694761200"; d="scan'208";a="902053918" Received: from joe-255.igk.intel.com (HELO localhost) ([10.91.220.57]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 22:48:05 -0700 From: Stanislaw Gruszka To: dri-devel@lists.freedesktop.org Subject: [PATCH] accel/ivpu: Disable PLL after VPU IP reset during FLR Date: Tue, 24 Oct 2023 07:50:22 +0200 Message-Id: <20231024055022.741080-1-stanislaw.gruszka@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stanislaw Gruszka , Oded Gabbay , Jeffrey Hugo , Jacek Lawrynowicz Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Jacek Lawrynowicz IP reset has to followed by ivpu_pll_disable() to properly enter reset state. Fixes: 828d63042aec ("accel/ivpu: Don't enter d0i3 during FLR") Cc: stable@vger.kernel.org Signed-off-by: Jacek Lawrynowicz Reviewed-by: Stanislaw Gruszka Signed-off-by: Stanislaw Gruszka --- drivers/accel/ivpu/ivpu_hw_37xx.c | 21 +++++++++++++++++++-- drivers/accel/ivpu/ivpu_hw_40xx.c | 23 ++++++++++++++++++++--- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c index 7e4e87aa7602..899369a3c5dc 100644 --- a/drivers/accel/ivpu/ivpu_hw_37xx.c +++ b/drivers/accel/ivpu/ivpu_hw_37xx.c @@ -598,7 +598,7 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev) return 0; } -static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) +static int ivpu_hw_37xx_ip_reset(struct ivpu_device *vdev) { int ret; u32 val; @@ -623,6 +623,23 @@ static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) return ret; } +static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) +{ + int ret = 0; + + if (ivpu_hw_37xx_ip_reset(vdev)) { + ivpu_err(vdev, "Failed to reset VPU IP\n"); + ret = -EIO; + } + + if (ivpu_pll_disable(vdev)) { + ivpu_err(vdev, "Failed to disable PLL\n"); + ret = -EIO; + } + + return ret; +} + static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev) { int ret; @@ -722,7 +739,7 @@ static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev) { int ret = 0; - if (!ivpu_hw_37xx_is_idle(vdev) && ivpu_hw_37xx_reset(vdev)) + if (!ivpu_hw_37xx_is_idle(vdev) && ivpu_hw_37xx_ip_reset(vdev)) ivpu_err(vdev, "Failed to reset the VPU\n"); if (ivpu_pll_disable(vdev)) { diff --git a/drivers/accel/ivpu/ivpu_hw_40xx.c b/drivers/accel/ivpu/ivpu_hw_40xx.c index e691c49c9841..b25d02dc541b 100644 --- a/drivers/accel/ivpu/ivpu_hw_40xx.c +++ b/drivers/accel/ivpu/ivpu_hw_40xx.c @@ -742,7 +742,7 @@ static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev) return 0; } -static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) +static int ivpu_hw_40xx_ip_reset(struct ivpu_device *vdev) { int ret; u32 val; @@ -764,6 +764,23 @@ static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) return ret; } +static int ivpu_hw_40xx_reset(struct ivpu_device *vdev) +{ + int ret = 0; + + if (ivpu_hw_40xx_ip_reset(vdev)) { + ivpu_err(vdev, "Failed to reset VPU IP\n"); + ret = -EIO; + } + + if (ivpu_pll_disable(vdev)) { + ivpu_err(vdev, "Failed to disable PLL\n"); + ret = -EIO; + } + + return ret; +} + static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev) { int ret; @@ -824,7 +841,7 @@ static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev) { int ret; - ret = ivpu_hw_40xx_reset(vdev); + ret = ivpu_hw_40xx_ip_reset(vdev); if (ret) { ivpu_err(vdev, "Failed to reset HW: %d\n", ret); return ret; @@ -902,7 +919,7 @@ static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev) { int ret = 0; - if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_reset(vdev)) + if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_ip_reset(vdev)) ivpu_warn(vdev, "Failed to reset the VPU\n"); if (ivpu_pll_disable(vdev)) {