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Wed, 25 Oct 2023 00:35:15 -0700 (PDT) From: Neil Armstrong Date: Wed, 25 Oct 2023 09:35:05 +0200 Subject: [PATCH 7/8] drm/msm: dsi: add support for DSI-PHY on SM8650 MIME-Version: 1.0 Message-Id: <20231025-topic-sm8650-upstream-mdss-v1-7-bb219b8c7a51@linaro.org> References: <20231025-topic-sm8650-upstream-mdss-v1-0-bb219b8c7a51@linaro.org> In-Reply-To: <20231025-topic-sm8650-upstream-mdss-v1-0-bb219b8c7a51@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Marek , Krishna Manikandan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2994; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=XWO1ll/O5SAbsuSLybzrQH6wpy3r8i5/kE9ugk0FOCE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlOMUoUEmSR+ZjythCe+M+cI29X4ttEvQXEp6dyj/C WxVnTQSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZTjFKAAKCRB33NvayMhJ0el5EA DHEoaO3OBaAsJwX/60zizjdw9SpfauMYI0hCcnezms29KLu4zki/fTD5kK+k9rLJeanPonoa/BDI/5 0Xk0eocLGavmDN7QHEH+YuzFWmvBJBjN2KP7FFdgbWjOfiaq1B4ggyVyZEJs+T7RSOOIf2l5oUnZKL FsnZosL2NarIjFz8lrSR3DU7raixkOKMpM3nYFhol0hOtANk3J+wv5j6bCkqcVxkmeRzbDdqiok7JB j5+1cDBcBfUi1+AvfAOrJ/cHx50u3umFiwZ+TtGx/4A931fuhtgTHQxatrhs6L5bqnQHN3CghqOBcO 1S4+y7bCbTlbQ89lw0gr2d2yp3A/5EYd5v5O2CTZ1UYml5YlDuyIEfFJlBvQeoIgKq4Lzkh4wBvRUI eon4nB0Mn2xULLzH7bkI8+QFQfBHmdAfYSJ2TpM2Lfdh1D7AcCPkttY7kFnqOEQQf41FKwKuKSAf9b 7knWyor266jdZ0b0S+fqyCmADy6q6kaCtlAcs1kRWTGv6VXW82jw256NizuYoFOLOzxboljA981oeb zbWwVjWcvtGcL3MnOeFA2zvvNmYW73iPaThGUKpjMkypolvWLGkTb0ceuJRUIz/VWdOq6D8Uy1sF4d WXiS9b+Z6r17Obic5KAD6I7x/QuMtNuX3UcBPhT7Vyyrxks9I113eXB4BXbA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add DSI PHY support for the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 05621e5e7d63..7612be6c3618 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_5nm_8450_cfgs }, { .compatible = "qcom,sm8550-dsi-phy-4nm", .data = &dsi_phy_4nm_8550_cfgs }, + { .compatible = "qcom,sm8650-dsi-phy-4nm", + .data = &dsi_phy_4nm_8650_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8b640d174785..e4275d3ad581 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 3b1ed02f644d..c66193f2dc0d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { { .supply = "vdds", .init_load_uA = 37550 }, }; +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 98000 }, +}; + static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { { .supply = "vdds", .init_load_uA = 97800 }, }; @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +};