| Message ID | 20231110101020.4067342-11-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC fractional bpp support | expand |
> Subject: [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per > DSC precision support > > Currently we iterate over the bpp_x16 in step of 16. > Use DSC fractional bpp precision supported by the sink to compute the > appropriate steps to iterate over the bpps. > LGTM. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index e7806fe11b9d..322046bb7d42 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -273,6 +273,8 @@ static int > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, > int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; > u8 dsc_max_bpc; > int min_compressed_bpp, max_compressed_bpp; > + int bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector- > >dp.dsc_dpcd); > + int bppx16_step; > > /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > if (DISPLAY_VER(i915) >= 12) > @@ -327,11 +329,16 @@ static int > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, > min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, > min_compressed_bpp, > crtc_state- > >pipe_bpp); > > + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) > + bppx16_step = 16; > + else > + bppx16_step = 16 / bppx16_incr; > + > slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, > > to_bpp_x16(max_compressed_bpp), > > to_bpp_x16(min_compressed_bpp), > limits, > - conn_state, 16, true); > + conn_state, bppx16_step, > true); > > if (slots < 0) > return slots; > -- > 2.40.1
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e7806fe11b9d..322046bb7d42 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -273,6 +273,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; u8 dsc_max_bpc; int min_compressed_bpp, max_compressed_bpp; + int bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); + int bppx16_step; /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ if (DISPLAY_VER(i915) >= 12) @@ -327,11 +329,16 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp, crtc_state->pipe_bpp); + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) + bppx16_step = 16; + else + bppx16_step = 16 / bppx16_incr; + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, to_bpp_x16(max_compressed_bpp), to_bpp_x16(min_compressed_bpp), limits, - conn_state, 16, true); + conn_state, bppx16_step, true); if (slots < 0) return slots;
Currently we iterate over the bpp_x16 in step of 16. Use DSC fractional bpp precision supported by the sink to compute the appropriate steps to iterate over the bpps. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)