| Message ID | 20231110101020.4067342-3-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC fractional bpp support | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Friday, November 10, 2023 3:40 PM > To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > Cc: Sharma, Swati2 <swati2.sharma@intel.com>; Kulkarni, Vandita > <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; > suijingfeng@loongson.cn > Subject: [PATCH 02/11] drm/i915/display: Store compressed bpp in U6.4 > format > > DSC parameter bits_per_pixel is stored in U6.4 format. > The 4 bits represent the fractional part of the bpp. > Currently we use compressed_bpp member of dsc structure to store only the > integral part of the bits_per_pixel. > To store the full bits_per_pixel along with the fractional part, > compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is > retrieved by simply right shifting the member compressed_bpp by 4. > > v2: > -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing with > compressed bpp. (Suraj) -Fix comment styling. (Suraj) > > v3: > -Add separate file for 6.4 fixed point helper(Jani, Nikula) -Add comment for > magic values(Suraj) > > v4: > -Fix checkpatch warnings caused by renaming(Suraj) > > v5: > -Rebase. > -Use existing helpers for conversion of bpp_int to bpp_x16 and vice versa. > LGTM. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++---- > drivers/gpu/drm/i915/display/intel_audio.c | 2 +- > drivers/gpu/drm/i915/display/intel_bios.c | 4 +-- > drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++-- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > .../drm/i915/display/intel_display_types.h | 3 ++- > drivers/gpu/drm/i915/display/intel_dp.c | 27 ++++++++++--------- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > drivers/gpu/drm/i915/display/intel_link_bw.c | 2 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-- > 10 files changed, 33 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index c4585e445198..481fcb650850 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder, > int bpp; > > if (crtc_state->dsc.compression_enable) > - bpp = crtc_state->dsc.compressed_bpp; > + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); > else > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi- > >pixel_format); > > @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct > intel_encoder *encoder, > * compressed and non-compressed bpp. > */ > if (crtc_state->dsc.compression_enable) { > - mul = crtc_state->dsc.compressed_bpp; > + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); > div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); > } > > @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct > intel_encoder *encoder, > int bpp, line_time_us, byte_clk_period_ns; > > if (crtc_state->dsc.compression_enable) > - bpp = crtc_state->dsc.compressed_bpp; > + bpp = to_bpp_int(crtc_state- > >dsc.compressed_bpp_x16); > else > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi- > >pixel_format); > > @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct > intel_encoder *encoder, > struct drm_display_mode *adjusted_mode = > &pipe_config->hw.adjusted_mode; > > - if (pipe_config->dsc.compressed_bpp) { > - int div = pipe_config->dsc.compressed_bpp; > + if (pipe_config->dsc.compressed_bpp_x16) { > + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); > int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi- > >pixel_format); > > adjusted_mode->crtc_htotal = > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c > b/drivers/gpu/drm/i915/display/intel_audio.c > index 19605264a35c..aa93ccd6c2aa 100644 > --- a/drivers/gpu/drm/i915/display/intel_audio.c > +++ b/drivers/gpu/drm/i915/display/intel_audio.c > @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct > intel_encoder *encoder, > h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; > h_total = crtc_state->hw.adjusted_mode.crtc_htotal; > pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; > - vdsc_bpp = crtc_state->dsc.compressed_bpp; > + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); > cdclk = i915->display.cdclk.hw.cdclk; > /* fec= 0.972261, using rounding multiplier of 1000000 */ > fec_coeff = 972261; > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c > b/drivers/gpu/drm/i915/display/intel_bios.c > index 719fb550342b..2fd72b2fd109 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, > > crtc_state->pipe_bpp = bpc * 3; > > - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, > - VBT_DSC_MAX_BPP(dsc- > >max_bpp)); > + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state- > >pipe_bpp, > + > VBT_DSC_MAX_BPP(dsc->max_bpp))); > > /* > * FIXME: This is ugly, and slice count should take DSC engine diff --git > a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index c4839c67cb0f..b93d1ad7936d 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct > intel_crtc_state *crtc_state) > * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner > Interface bits > */ > int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : > 24; > - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * > pixel_clock) / > - (2 * bigjoiner_interface_bits); > + int min_cdclk_bj = > + (to_bpp_int_roundup(crtc_state- > >dsc.compressed_bpp_x16) * > + pixel_clock) / (2 * bigjoiner_interface_bits); > > min_cdclk = max(min_cdclk, min_cdclk_bj); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 3effafcbb411..b4a8e3087e50 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct > intel_crtc_state *current_config, > > PIPE_CONF_CHECK_I(dsc.compression_enable); > PIPE_CONF_CHECK_I(dsc.dsc_split); > - PIPE_CONF_CHECK_I(dsc.compressed_bpp); > + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); > > PIPE_CONF_CHECK_BOOL(splitter.enable); > PIPE_CONF_CHECK_I(splitter.link_count); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 926bf9c1a3ed..19e7e6e2e7a6 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1362,7 +1362,8 @@ struct intel_crtc_state { > struct { > bool compression_enable; > bool dsc_split; > - u16 compressed_bpp; > + /* Compressed Bpp in U6.4 format (first 4 bits for fractional > part) */ > + u16 compressed_bpp_x16; > u8 slice_count; > struct drm_dsc_config config; > } dsc; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 37d7c9c2d695..4ad3718c3c7d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp > *intel_dp, > valid_dsc_bpp[i], > timeslots); > if (ret == 0) { > - pipe_config->dsc.compressed_bpp = > valid_dsc_bpp[i]; > + pipe_config->dsc.compressed_bpp_x16 = > + to_bpp_x16(valid_dsc_bpp[i]); > return 0; > } > } > @@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp > *intel_dp, > compressed_bpp, > timeslots); > if (ret == 0) { > - pipe_config->dsc.compressed_bpp = > compressed_bpp; > + pipe_config->dsc.compressed_bpp_x16 = > + to_bpp_x16(compressed_bpp); > return 0; > } > } > @@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct > intel_dp *intel_dp, > /* Compressed BPP should be less than the Input DSC bpp */ > dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); > > - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, > dsc_max_bpp); > + pipe_config->dsc.compressed_bpp_x16 = > + to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp)); > > pipe_config->pipe_bpp = pipe_bpp; > > @@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp > *intel_dp, > ret = intel_dp_dsc_compute_params(connector, pipe_config); > if (ret < 0) { > drm_dbg_kms(&dev_priv->drm, > - "Cannot compute valid DSC parameters for Input > Bpp = %d " > - "Compressed BPP = %d\n", > + "Cannot compute valid DSC parameters for Input > Bpp = %d" > + "Compressed BPP = " BPP_X16_FMT "\n", > pipe_config->pipe_bpp, > - pipe_config->dsc.compressed_bpp); > + BPP_X16_ARGS(pipe_config- > >dsc.compressed_bpp_x16)); > return ret; > } > > pipe_config->dsc.compression_enable = true; > drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = > %d " > - "Compressed Bpp = %d Slice Count = %d\n", > + "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n", > pipe_config->pipe_bpp, > - pipe_config->dsc.compressed_bpp, > + BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), > pipe_config->dsc.slice_count); > > return 0; > @@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct > intel_encoder *encoder, > > if (pipe_config->dsc.compression_enable) { > drm_dbg_kms(&i915->drm, > - "DP lane count %d clock %d Input bpp %d > Compressed bpp %d\n", > + "DP lane count %d clock %d Input bpp %d > Compressed bpp " > +BPP_X16_FMT "\n", > pipe_config->lane_count, pipe_config->port_clock, > pipe_config->pipe_bpp, > - pipe_config->dsc.compressed_bpp); > + BPP_X16_ARGS(pipe_config- > >dsc.compressed_bpp_x16)); > > drm_dbg_kms(&i915->drm, > "DP link rate required %i available %i\n", > intel_dp_link_required(adjusted_mode->crtc_clock, > - pipe_config- > >dsc.compressed_bpp), > + > to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)), > intel_dp_max_data_rate(pipe_config->port_clock, > pipe_config->lane_count)); > } else { > @@ -2838,7 +2841,7 @@ intel_dp_compute_config(struct intel_encoder > *encoder, > drm_dp_enhanced_frame_cap(intel_dp->dpcd); > > if (pipe_config->dsc.compression_enable) > - link_bpp = pipe_config->dsc.compressed_bpp; > + link_bpp = to_bpp_int(pipe_config- > >dsc.compressed_bpp_x16); > else > link_bpp = intel_dp_output_bpp(pipe_config- > >output_format, > pipe_config->pipe_bpp); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 107f7418ddc5..31461ea25f7c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -227,7 +227,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct > intel_encoder *encoder, > if (!dsc) > crtc_state->pipe_bpp = bpp; > else > - crtc_state->dsc.compressed_bpp = bpp; > + crtc_state->dsc.compressed_bpp_x16 = > to_bpp_x16(bpp); > drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d > dsc %d\n", slots, bpp, dsc); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c > b/drivers/gpu/drm/i915/display/intel_link_bw.c > index 390db5c0c24a..02a0af2aa5ba 100644 > --- a/drivers/gpu/drm/i915/display/intel_link_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c > @@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state > *state, > return PTR_ERR(crtc_state); > > if (crtc_state->dsc.compression_enable) > - link_bpp = crtc_state->dsc.compressed_bpp; > + link_bpp = crtc_state->dsc.compressed_bpp_x16; > else > /* > * TODO: for YUV420 the actual link bpp is only half > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 6757dbae9ee5..3a1ed574edbb 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state > *pipe_config) > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; > - u16 compressed_bpp = pipe_config->dsc.compressed_bpp; > + u16 compressed_bpp = to_bpp_int(pipe_config- > >dsc.compressed_bpp_x16); > int err; > int ret; > > @@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct > intel_crtc_state *crtc_state) > if (vdsc_cfg->native_420) > vdsc_cfg->bits_per_pixel >>= 1; > > - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; > + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel; > > /* PPS 2 */ > pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); > -- > 2.40.1
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index c4585e445198..481fcb650850 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder, int bpp; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * compressed and non-compressed bpp. */ if (crtc_state->dsc.compression_enable) { - mul = crtc_state->dsc.compressed_bpp; + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); } @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, int bpp, line_time_us, byte_clk_period_ns; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - if (pipe_config->dsc.compressed_bpp) { - int div = pipe_config->dsc.compressed_bpp; + if (pipe_config->dsc.compressed_bpp_x16) { + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); adjusted_mode->crtc_htotal = diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 19605264a35c..aa93ccd6c2aa 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = crtc_state->dsc.compressed_bpp; + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 719fb550342b..2fd72b2fd109 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->pipe_bpp = bpc * 3; - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, - VBT_DSC_MAX_BPP(dsc->max_bpp)); + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp, + VBT_DSC_MAX_BPP(dsc->max_bpp))); /* * FIXME: This is ugly, and slice count should take DSC engine diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c4839c67cb0f..b93d1ad7936d 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits */ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24; - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) / - (2 * bigjoiner_interface_bits); + int min_cdclk_bj = + (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * + pixel_clock) / (2 * bigjoiner_interface_bits); min_cdclk = max(min_cdclk, min_cdclk_bj); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3effafcbb411..b4a8e3087e50 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(dsc.compression_enable); PIPE_CONF_CHECK_I(dsc.dsc_split); - PIPE_CONF_CHECK_I(dsc.compressed_bpp); + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_I(splitter.link_count); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 926bf9c1a3ed..19e7e6e2e7a6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1362,7 +1362,8 @@ struct intel_crtc_state { struct { bool compression_enable; bool dsc_split; - u16 compressed_bpp; + /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ + u16 compressed_bpp_x16; u8 slice_count; struct drm_dsc_config config; } dsc; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 37d7c9c2d695..4ad3718c3c7d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, valid_dsc_bpp[i], timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i]; + pipe_config->dsc.compressed_bpp_x16 = + to_bpp_x16(valid_dsc_bpp[i]); return 0; } } @@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, compressed_bpp, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp = compressed_bpp; + pipe_config->dsc.compressed_bpp_x16 = + to_bpp_x16(compressed_bpp); return 0; } } @@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, /* Compressed BPP should be less than the Input DSC bpp */ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp); + pipe_config->dsc.compressed_bpp_x16 = + to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp)); pipe_config->pipe_bpp = pipe_bpp; @@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { drm_dbg_kms(&dev_priv->drm, - "Cannot compute valid DSC parameters for Input Bpp = %d " - "Compressed BPP = %d\n", + "Cannot compute valid DSC parameters for Input Bpp = %d" + "Compressed BPP = " BPP_X16_FMT "\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); return ret; } pipe_config->dsc.compression_enable = true; drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " - "Compressed Bpp = %d Slice Count = %d\n", + "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp, + BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), pipe_config->dsc.slice_count); return 0; @@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (pipe_config->dsc.compression_enable) { drm_dbg_kms(&i915->drm, - "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", + "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n", pipe_config->lane_count, pipe_config->port_clock, pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); drm_dbg_kms(&i915->drm, "DP link rate required %i available %i\n", intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->dsc.compressed_bpp), + to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)), intel_dp_max_data_rate(pipe_config->port_clock, pipe_config->lane_count)); } else { @@ -2838,7 +2841,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, drm_dp_enhanced_frame_cap(intel_dp->dpcd); if (pipe_config->dsc.compression_enable) - link_bpp = pipe_config->dsc.compressed_bpp; + link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); else link_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_config->pipe_bpp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 107f7418ddc5..31461ea25f7c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -227,7 +227,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, if (!dsc) crtc_state->pipe_bpp = bpp; else - crtc_state->dsc.compressed_bpp = bpp; + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp); drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc); } diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c index 390db5c0c24a..02a0af2aa5ba 100644 --- a/drivers/gpu/drm/i915/display/intel_link_bw.c +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c @@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, return PTR_ERR(crtc_state); if (crtc_state->dsc.compression_enable) - link_bpp = crtc_state->dsc.compressed_bpp; + link_bpp = crtc_state->dsc.compressed_bpp_x16; else /* * TODO: for YUV420 the actual link bpp is only half diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 6757dbae9ee5..3a1ed574edbb 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; - u16 compressed_bpp = pipe_config->dsc.compressed_bpp; + u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); int err; int ret; @@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) if (vdsc_cfg->native_420) vdsc_cfg->bits_per_pixel >>= 1; - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel; /* PPS 2 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);