| Message ID | 20231121185556.45770-1-alan.previn.teres.alexis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] drm/i915/pxp: Add missing tag for Wa_14019159160 | expand |
On 11/21/2023 10:55, Alan Previn wrote: > Add missing tag for "Wa_14019159160 - Case 2" (for existing > PXP code that ensures run alone mode bit is set to allow > PxP-decryption. > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 7c367ba8d9dc..c758fe4906a5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -863,8 +863,10 @@ static bool ctx_needs_runalone(const struct intel_context *ce) > bool ctx_is_protected = false; > > /* > + * Wa_140191591606 - Case 2: mtl Too many sixes. > * On MTL and newer platforms, protected contexts require setting Probably better to say 'On some platforms'. The current wording implies this is an intentional hardware change that will be carried forward rather than a bug requiring a workaround which will (hopefully) be fixed on some future platform. > - * the LRC run-alone bit or else the encryption will not happen. > + * the LRC run-alone bit or else the encryption/decryption will not happen. > + * NOTE: Case 2 only applies to PXP use-case of said workaround. > */ > if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && Likewise, this should only test for the explicit platforms listed in the w/a definition rather than assume all future platforms. John. > (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) { > > base-commit: dbdb47c227dc21b7bf98ada039bf42aac4b58b8b
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7c367ba8d9dc..c758fe4906a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -863,8 +863,10 @@ static bool ctx_needs_runalone(const struct intel_context *ce) bool ctx_is_protected = false; /* + * Wa_140191591606 - Case 2: mtl * On MTL and newer platforms, protected contexts require setting - * the LRC run-alone bit or else the encryption will not happen. + * the LRC run-alone bit or else the encryption/decryption will not happen. + * NOTE: Case 2 only applies to PXP use-case of said workaround. */ if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {
Add missing tag for "Wa_14019159160 - Case 2" (for existing PXP code that ensures run alone mode bit is set to allow PxP-decryption. Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) base-commit: dbdb47c227dc21b7bf98ada039bf42aac4b58b8b