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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:17:46 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:30 +0100 Subject: [PATCH 02/12] dt-bindings: display: msm: Add reg bus and rotator interconnects MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-2-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=1875; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=AFFsjfQ/BWb6zbEE2kIE5M6+YBHmlQ+rokF2C+2Kd04=; b=Ko21H+lWGGl59y8qJsZ+LTUw0AWkhTziUlqwg4+lQP0Zq18rNp2fD1omovB6ZeBmhVmjSNMTp wKdjaAGzz5nAy1P3zo5fSusiUSJLqx/3Pre4Gi7Q7gCCuziLVKdW0lH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , iommu@lists.linux.dev, Marijn Suijten , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are other connection paths: - a path that connects rotator block to the DDR. - a path that needs to be handled to ensure MDSS register access functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG interconnect. Describe these paths bindings to allow using them in device trees and in the driver Signed-off-by: Dmitry Baryshkov [Konrad: rework for one vs two MDP paths] Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/mdss-common.yaml | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index f69196e4cc76..c6305a6e0334 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -61,17 +61,27 @@ properties: ranges: true + # This is not a perfect description, but it's impossible to discern and match + # the entries like we do with interconnect-names interconnects: minItems: 1 items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - minItems: 1 - items: - - const: mdp0-mem - - const: mdp1-mem + oneOf: + - minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + + - minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: cpu-cfg resets: items: