From patchwork Tue Dec 5 22:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13480826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81230C10F05 for ; Tue, 5 Dec 2023 22:06:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E8B2310E638; Tue, 5 Dec 2023 22:06:29 +0000 (UTC) Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0ADF910E638; Tue, 5 Dec 2023 22:06:28 +0000 (UTC) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1d08a924fcfso27334275ad.2; Tue, 05 Dec 2023 14:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701813986; x=1702418786; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZfGTVvgq7n98tDeI+oB8ofi/GtnZCvkbAjomQZwW1cY=; b=E4A6sxYo3L8yY6rybsT7p8N6gl45Rjp5dnjlcYPeDoj0EdukpBVPYHyLcSJzP39Zqi I2Uleyiy1Sljon9ZWR5qjBhb/tGY+/chsBX7UG3Nrm+gdEal1VdGZBxA11Z1QJK+i+HJ B4ryEteMItEk5om+zHnHy/fFHr+ddDVQ19L5VvP/YTUWcmLM3yb39AuFj9GkUt4rDEp0 cmUc59hniJNDOwhuvaOvNaBRkdt99ZnoJVeOs7S4XIW29Rt+DUARNlrGwhuWBYU/P1YW dXlUNvEMDfk56mFFDHfYN8Xp6SsBdH0vzcE9WTHhdIj1ababbHv0ejhpoDMC7wpehWPs YcxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701813986; x=1702418786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZfGTVvgq7n98tDeI+oB8ofi/GtnZCvkbAjomQZwW1cY=; b=JTW2teXA2yhpiW/1HTthWM1QiIDcJDAydHE/CcBCQw94R0Ndzs3SAe6QGP6MnDY9QE MJyvz6bT12ANXXRnOg7Zjz9PWOZH4aCRCD4smxIVdZDvkIgusWb7oVsHip8SXUUZ+IUA dj1qeVMv8iX3JRhgPLS9942xC4m1JlGN5A/qLz2EibHP8W2Ml3va2megMRpIu4kZRJow 7O2/k3AY3Pog0c/iMjKU6V9GmcBkKM9lBFewUwUu+QBSqr/MVvu2pRaL1jl3TyZmM/5P 0QK1VMwqzt3JGN30VqIZzM3g1NEggiFd7M+z1V0IM6O3b9iUNbcf76O7MJV8W3ikhltO +PCw== X-Gm-Message-State: AOJu0YwOI2ox4XtG5GEOKqNGpqONuVHnGNQBiJid0Calri9+OMLRLsdi 6XpquCVpFlKzRrG+/I3+3JQDR+rBtME= X-Google-Smtp-Source: AGHT+IETLfRI/+vuaoElPPv+EjDm+Sp72Ua1AScWFXqXsgoOIGdLwWdKpoXF/M6bbHYTOeLLye0xfw== X-Received: by 2002:a17:902:eccd:b0:1d0:c906:f5e0 with SMTP id a13-20020a170902eccd00b001d0c906f5e0mr1345297plh.72.1701813986187; Tue, 05 Dec 2023 14:06:26 -0800 (PST) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id mi7-20020a17090b4b4700b00286a708cd07sm4189353pjb.57.2023.12.05.14.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 14:06:25 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Subject: [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Date: Tue, 5 Dec 2023 14:03:30 -0800 Message-ID: <20231205220526.417719-5-robdclark@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231205220526.417719-1-robdclark@gmail.com> References: <20231205220526.417719-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Akhil P Oommen , linux-arm-msm@vger.kernel.org, Bjorn Andersson , Abhinav Kumar , Douglas Anderson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Marijn Suijten , freedreno@lists.freedesktop.org, open list Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Introduce a6xx_info where we can stash gen specific stuff without polluting the toplevel adreno_info struct. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +++++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++- 4 files changed, 58 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index a35d4c112a61..3fb9e249567a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -7,6 +7,7 @@ */ #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" @@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", - .hwcg = a612_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a612_hwcg, + }, /* * There are (at least) three SoCs implementing A610: SM6125 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does @@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .a6xx = &(struct a6xx_info) { + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 169, 1 }, @@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 138, 1 }, @@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 190, 1 }, @@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", - .hwcg = a615_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a615_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 120, 4 }, @@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", - .hwcg = a630_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a630_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, @@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, { 1, 1 }, @@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", - .hwcg = a650_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a650_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x06030500), @@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", - .hwcg = a660_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a660_hwcg, + }, .address_space_size = SZ_16G, .speedbins = ADRENO_SPEEDBINS( { 0, 0 }, @@ -663,7 +684,9 @@ const struct adreno_info a6xx_gpus[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", - .hwcg = a640_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a640_hwcg, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, @@ -677,7 +700,9 @@ const struct adreno_info a6xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", - .hwcg = a690_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a690_hwcg, + }, .address_space_size = SZ_16G, }, { /* sentinal */ @@ -822,7 +847,9 @@ const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a730_zap.mdt", - .hwcg = a730_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a730_hwcg, + }, .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ @@ -837,7 +864,9 @@ const struct adreno_info a7xx_gpus[] = { ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", - .hwcg = a740_hwcg, + .a6xx = &(struct a6xx_info) { + .hwcg = a740_hwcg, + }, .address_space_size = SZ_16G, }, { /* sentinal */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index e0414d0753ad..a064eb42eedd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!adreno_gpu->info->a6xx->hwcg) return; if (adreno_is_a630(adreno_gpu)) @@ -434,7 +434,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); - for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) + for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 34822b080759..1840c1f3308e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,15 @@ extern bool hang_debug; +/** + * struct a6xx_info - a6xx specific information from device table + * + * @hwcg: hw clock gating register sequence + */ +struct a6xx_info { + const struct adreno_reglist *hwcg; +}; + struct a6xx_gpu { struct adreno_gpu base; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 5d094c5ec363..cba53203de98 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -81,6 +81,8 @@ struct adreno_speedbin { uint16_t speedbin; }; +struct a6xx_info; + struct adreno_info { const char *machine; /** @@ -97,7 +99,9 @@ struct adreno_info { struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw; u32 inactive_period; - const struct adreno_reglist *hwcg; + union { + const struct a6xx_info *a6xx; + }; u64 address_space_size; /** * @speedbins: Optional table of fuse to speedbin mappings