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[78.45.66.209]) by smtp.gmail.com with ESMTPSA id n13-20020a05640204cd00b0055971af7a23sm2258418edw.95.2024.01.16.19.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 19:12:20 -0800 (PST) From: Erico Nunes To: Qiang Yu , dri-devel@lists.freedesktop.org, lima@lists.freedesktop.org Subject: [PATCH v1 2/6] drm/lima: reset async_reset on pp hard reset Date: Wed, 17 Jan 2024 04:12:08 +0100 Message-ID: <20240117031212.1104034-3-nunes.erico@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240117031212.1104034-1-nunes.erico@gmail.com> References: <20240117031212.1104034-1-nunes.erico@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Zimmermann , linux-kernel@vger.kernel.org, Maxime Ripard , christian.koenig@amd.com, anarsoul@gmail.com, Daniel Vetter , David Airlie , Sumit Semwal , Erico Nunes Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Lima pp jobs use an async reset to avoid having to wait for the soft reset right after a job. The soft reset is done at the end of a job and a reset_complete flag is expected to be set at the next job. However, in case the user runs into a job timeout from any application, a hard reset is issued to the hardware. This hard reset clears the reset_complete flag, which causes an error message to show up before the next job. This is probably harmless for the execution but can be very confusing to debug, as it blames a reset timeout on the next application to submit a job. Reset the async_reset flag when doing the hard reset so that we don't get that message. Signed-off-by: Erico Nunes Reviewed-by: Vasily Khoruzhick --- drivers/gpu/drm/lima/lima_pp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/lima/lima_pp.c b/drivers/gpu/drm/lima/lima_pp.c index a5c95bed08c0..a8f8f63b8295 100644 --- a/drivers/gpu/drm/lima/lima_pp.c +++ b/drivers/gpu/drm/lima/lima_pp.c @@ -191,6 +191,13 @@ static int lima_pp_hard_reset(struct lima_ip *ip) pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0); pp_write(LIMA_PP_INT_CLEAR, LIMA_PP_IRQ_MASK_ALL); pp_write(LIMA_PP_INT_MASK, LIMA_PP_IRQ_MASK_USED); + + /* + * if there was an async soft reset queued, + * don't wait for it in the next job + */ + ip->data.async_reset = false; + return 0; }