| Message ID | 20240123102850.390126-7-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Add Display Port tunnel BW allocation support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre > Deak > Sent: Tuesday, January 23, 2024 3:59 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org > Subject: [PATCH 06/19] drm/i915/dp: Export > intel_dp_max_common_rate/lane_count() > > Export intel_dp_max_common_rate() and intel_dp_max_lane_count() used by a > follow-up patch enabling the DP tunnel BW allocation mode. Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0a5c60428ffb7..f40706c5d1aad 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -309,7 +309,7 @@ static int intel_dp_common_rate(struct intel_dp > *intel_dp, int index) } > > /* Theoretical max between source and sink */ -static int > intel_dp_max_common_rate(struct intel_dp *intel_dp) > +int intel_dp_max_common_rate(struct intel_dp *intel_dp) > { > return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - > 1); } @@ -326,7 +326,7 @@ static int intel_dp_max_source_lane_count(struct > intel_digital_port *dig_port) } > > /* Theoretical max between source and sink */ -static int > intel_dp_max_common_lane_count(struct intel_dp *intel_dp) > +int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) > { > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > int source_max = intel_dp_max_source_lane_count(dig_port); > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index 37274e3c2902f..a7906d8738c4a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -104,6 +104,8 @@ int intel_dp_max_link_rate(struct intel_dp *intel_dp); int > intel_dp_max_lane_count(struct intel_dp *intel_dp); int > intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int > intel_dp_rate_select(struct intel_dp *intel_dp, int rate); > +int intel_dp_max_common_rate(struct intel_dp *intel_dp); int > +intel_dp_max_common_lane_count(struct intel_dp *intel_dp); > > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, > u8 *link_bw, u8 *rate_select); > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0a5c60428ffb7..f40706c5d1aad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -309,7 +309,7 @@ static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) } /* Theoretical max between source and sink */ -static int intel_dp_max_common_rate(struct intel_dp *intel_dp) +int intel_dp_max_common_rate(struct intel_dp *intel_dp) { return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); } @@ -326,7 +326,7 @@ static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) } /* Theoretical max between source and sink */ -static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) +int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); int source_max = intel_dp_max_source_lane_count(dig_port); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 37274e3c2902f..a7906d8738c4a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -104,6 +104,8 @@ int intel_dp_max_link_rate(struct intel_dp *intel_dp); int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); +int intel_dp_max_common_rate(struct intel_dp *intel_dp); +int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select);
Export intel_dp_max_common_rate() and intel_dp_max_lane_count() used by a follow-up patch enabling the DP tunnel BW allocation mode. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)