From patchwork Tue Feb 6 11:45:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 13547098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A8DAC4829A for ; Tue, 6 Feb 2024 11:46:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BDDE112ADD; Tue, 6 Feb 2024 11:46:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=foss.st.com header.i=@foss.st.com header.b="eHQtQA96"; dkim-atps=neutral Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by gabe.freedesktop.org (Postfix) with ESMTPS id 020E5112ADD for ; Tue, 6 Feb 2024 11:46:08 +0000 (UTC) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 416BZYR9004202; Tue, 6 Feb 2024 12:45:58 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=selector1; bh=DnsKquutEGOQewPoi6J/BDbXg1mh4kqRqxYNbt4LG2M =; b=eHQtQA96WcWUai0vRbpWi1UKZYEMv8iy9OmWS1EUh9m9KxI8eIEqxCDXOrr wWrih62a/7cP7QViwTNDvbALHuJsQSmzgxfnyj6iNTRq2/tc+FZ0n4r3syiHArB3 vufbVf7IX130sWvq4lDKnaFkJLmFLwWyYfVWisl5YcZrfpkSEmJFDFOv8IfWEbo/ 7YeKqH/8LzQrvBQSBYnpeqQRKIldIaAltpCXDJbGB4qJsrzKVTiwDo8c8UvfydxD OXoYEZevQnIoGQlfpN2XVV17wT6FRtQN1M9gKBZ8eCXMhwEAHVmE5PsrOgQTUcbO KsrzMsP99QOlzZKz5zxRePOjcdw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3w1eypb837-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 12:45:57 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6A2CB100056; Tue, 6 Feb 2024 12:45:57 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6105123D408; Tue, 6 Feb 2024 12:45:57 +0100 (CET) Received: from localhost (10.129.178.155) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 6 Feb 2024 12:45:55 +0100 From: Raphael Gallais-Pou Date: Tue, 6 Feb 2024 12:45:36 +0100 Subject: [PATCH v5 3/3] drm/stm: ltdc: add lvds pixel clock MIME-Version: 1.0 Message-ID: <20240206-lvds-v5-3-bd16797b0f09@foss.st.com> References: <20240206-lvds-v5-0-bd16797b0f09@foss.st.com> In-Reply-To: <20240206-lvds-v5-0-bd16797b0f09@foss.st.com> To: David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Yannick Fertre , Philippe Cornu , Philipp Zabel CC: , , , , , Raphael Gallais-Pou X-Mailer: b4 0.12.4 X-Originating-IP: [10.129.178.155] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-06_04,2024-01-31_01,2023-05-22_02 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The STM32MP25x display subsystem presents a mux which feeds the loopback pixel clock of the current bridge in use into the LTDC. This mux is only accessible through sysconfig registers which is not yet available in the STM32MP25x common clock framework. While waiting for a complete update of the clock framework, this would allow to use the LVDS. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Yannick Fertre --- Changes in v2: - Fixed my address - Fixed smatch warning --- drivers/gpu/drm/stm/ltdc.c | 19 +++++++++++++++++++ drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 5576fdae4962..23011a8913bd 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max = target + CLK_TOLERANCE_HZ; int result; + if (ldev->lvds_clk) { + result = clk_round_rate(ldev->lvds_clk, target); + DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n", + target, result); + } + result = clk_round_rate(ldev->pixel_clk, target); DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev) DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } int ltdc_resume(struct drm_device *ddev) @@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev) DRM_ERROR("failed to enable pixel clock (%d)\n", ret); return ret; } + if (ldev->lvds_clk) { + if (clk_prepare_enable(ldev->lvds_clk)) { + clk_disable_unprepare(ldev->pixel_clk); + DRM_ERROR("Unable to prepare lvds clock\n"); + return -ENODEV; + } + } return 0; } @@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev) } } + ldev->lvds_clk = devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk = NULL; + rstc = devm_reset_control_get_exclusive(dev, NULL); mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdb..4a60ce5b610c 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -44,6 +44,7 @@ struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *lvds_clk; /* lvds pixel clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; u32 irq_status;