[V2,2/2] drm/bridge: samsung-dsim: Fix porch calcalcuation rounding

Commit Message

Adam Ford Feb. 11, 2024, 11:09 p.m. UTC

When using video sync pulses, the HFP, HBP, and HSA are divided between
the available lanes if there is more than one lane.  For certain
timings and lane configurations, the HFP may not be evenly divisible.
If the HFP is rounded down, it ends up being too small which can cause
some monitors to not sync properly. In these instances, adjust htotal
and hsync to round the HFP up, and recalculate the htotal.

Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
Signed-off-by: Adam Ford <[e-mail]>
---
V2:  No changes

Comments

Adam Ford April 16, 2024, 12:15 p.m. UTC | #1

On Sun, Feb 11, 2024 at 5:09 PM Adam Ford <[e-mail]> wrote:
>
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane.  For certain
> timings and lane configurations, the HFP may not be evenly divisible.
> If the HFP is rounded down, it ends up being too small which can cause
> some monitors to not sync properly. In these instances, adjust htotal
> and hsync to round the HFP up, and recalculate the htotal.
>

Marek V and Marek S,

Would either of you be willing to test that this doesn't break your
applications?

thanks

adam

> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> Signed-off-by: Adam Ford <[e-mail]>
> ---
> V2:  No changes
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 8476650c477c..52939211fe93 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>                 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>         }
>
> +       /*
> +        * When using video sync pulses, the HFP, HBP, and HSA are divided between
> +        * the available lanes if there is more than one lane.  For certain
> +        * timings and lane configurations, the HFP may not be evenly divisible.
> +        * If the HFP is rounded down, it ends up being too small which can cause
> +        * some monitors to not sync properly. In these instances, adjust htotal
> +        * and hsync to round the HFP up, and recalculate the htotal. Through trial
> +        * and error, it appears that the HBP and HSA do not appearto need the same
> +        * correction that HFP does.
> +        */
> +       if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
> +               int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
> +               int remainder = hfp % dsi->lanes;
> +
> +               if (remainder) {
> +                       adjusted_mode->hsync_start += remainder;
> +                       adjusted_mode->hsync_end   += remainder;
> +                       adjusted_mode->htotal      += remainder;
> +               }
> +       }
> +
>         return 0;
>  }
>
> --
> 2.43.0
>

Marek Vasut April 21, 2024, 2:06 p.m. UTC | #2

On 2/12/24 12:09 AM, Adam Ford wrote:
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane.  For certain
> timings and lane configurations, the HFP may not be evenly divisible.
> If the HFP is rounded down, it ends up being too small which can cause
> some monitors to not sync properly. In these instances, adjust htotal
> and hsync to round the HFP up, and recalculate the htotal.
> 
> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> Signed-off-by: Adam Ford <[e-mail]>
> ---
> V2:  No changes
> 
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 8476650c477c..52939211fe93 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>   		adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>   	}
>   
> +	/*
> +	 * When using video sync pulses, the HFP, HBP, and HSA are divided between
> +	 * the available lanes if there is more than one lane.  For certain
> +	 * timings and lane configurations, the HFP may not be evenly divisible.
> +	 * If the HFP is rounded down, it ends up being too small which can cause
> +	 * some monitors to not sync properly. In these instances, adjust htotal
> +	 * and hsync to round the HFP up, and recalculate the htotal. Through trial
> +	 * and error, it appears that the HBP and HSA do not appearto need the same
> +	 * correction that HFP does.
> +	 */
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {

Does this also apply to mode with sync events (I suspect it does), so 
the condition here should likely be if (!...burst mode) , right ?

Adam Ford April 22, 2024, 12:09 p.m. UTC | #3

On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut <[e-mail]> wrote:
>
> On 2/12/24 12:09 AM, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane.  For certain
> > timings and lane configurations, the HFP may not be evenly divisible.
> > If the HFP is rounded down, it ends up being too small which can cause
> > some monitors to not sync properly. In these instances, adjust htotal
> > and hsync to round the HFP up, and recalculate the htotal.
> >
> > Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> > Signed-off-by: Adam Ford <[e-mail]>
> > ---
> > V2:  No changes
> >
> > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> > index 8476650c477c..52939211fe93 100644
> > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> >               adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> >       }
> >
> > +     /*
> > +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
> > +      * the available lanes if there is more than one lane.  For certain
> > +      * timings and lane configurations, the HFP may not be evenly divisible.
> > +      * If the HFP is rounded down, it ends up being too small which can cause
> > +      * some monitors to not sync properly. In these instances, adjust htotal
> > +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
> > +      * and error, it appears that the HBP and HSA do not appearto need the same
> > +      * correction that HFP does.
> > +      */
> > +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
>
> Does this also apply to mode with sync events (I suspect it does), so
> the condition here should likely be if (!...burst mode) , right ?

Thanks for the review!

I was only able to test it with the DSI->ADV6535 bridge, and I'll
admit I don't know a lot about DSI interface since I don't have a copy
of the spec to read.

Are you proposing this should be:

 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && dsi->lanes > 1) {

I just want to make sure I understand what you're requesting.

thanks

adam

Marek Vasut April 22, 2024, 12:30 p.m. UTC | #4

On 4/22/24 2:09 PM, Adam Ford wrote:
> On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut <[e-mail]> wrote:
>>
>> On 2/12/24 12:09 AM, Adam Ford wrote:
>>> When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> the available lanes if there is more than one lane.  For certain
>>> timings and lane configurations, the HFP may not be evenly divisible.
>>> If the HFP is rounded down, it ends up being too small which can cause
>>> some monitors to not sync properly. In these instances, adjust htotal
>>> and hsync to round the HFP up, and recalculate the htotal.
>>>
>>> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
>>> Signed-off-by: Adam Ford <[e-mail]>
>>> ---
>>> V2:  No changes
>>>
>>> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> index 8476650c477c..52939211fe93 100644
>>> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
>>> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>>>                adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>>>        }
>>>
>>> +     /*
>>> +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> +      * the available lanes if there is more than one lane.  For certain
>>> +      * timings and lane configurations, the HFP may not be evenly divisible.
>>> +      * If the HFP is rounded down, it ends up being too small which can cause
>>> +      * some monitors to not sync properly. In these instances, adjust htotal
>>> +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
>>> +      * and error, it appears that the HBP and HSA do not appearto need the same
>>> +      * correction that HFP does.
>>> +      */
>>> +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
>>
>> Does this also apply to mode with sync events (I suspect it does), so
>> the condition here should likely be if (!...burst mode) , right ?
> 
> Thanks for the review!
> 
> I was only able to test it with the DSI->ADV6535 bridge, and I'll
> admit I don't know a lot about DSI interface since I don't have a copy
> of the spec to read.
> 
> Are you proposing this should be:
> 
>   if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && dsi->lanes > 1) {
> 
> I just want to make sure I understand what you're requesting.

Yes, exactly this.

Adam Ford April 22, 2024, 1:04 p.m. UTC | #5

On Mon, Apr 22, 2024 at 8:01 AM Marek Vasut <[e-mail]> wrote:
>
> On 4/22/24 2:09 PM, Adam Ford wrote:
> > On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut <[e-mail]> wrote:
> >>
> >> On 2/12/24 12:09 AM, Adam Ford wrote:
> >>> When using video sync pulses, the HFP, HBP, and HSA are divided between
> >>> the available lanes if there is more than one lane.  For certain
> >>> timings and lane configurations, the HFP may not be evenly divisible.
> >>> If the HFP is rounded down, it ends up being too small which can cause
> >>> some monitors to not sync properly. In these instances, adjust htotal
> >>> and hsync to round the HFP up, and recalculate the htotal.
> >>>
> >>> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> >>> Signed-off-by: Adam Ford <[e-mail]>
> >>> ---
> >>> V2:  No changes
> >>>
> >>> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> >>> index 8476650c477c..52939211fe93 100644
> >>> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> >>> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> >>> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> >>>                adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> >>>        }
> >>>
> >>> +     /*
> >>> +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
> >>> +      * the available lanes if there is more than one lane.  For certain
> >>> +      * timings and lane configurations, the HFP may not be evenly divisible.
> >>> +      * If the HFP is rounded down, it ends up being too small which can cause
> >>> +      * some monitors to not sync properly. In these instances, adjust htotal
> >>> +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
> >>> +      * and error, it appears that the HBP and HSA do not appearto need the same
> >>> +      * correction that HFP does.
> >>> +      */
> >>> +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
> >>
> >> Does this also apply to mode with sync events (I suspect it does), so
> >> the condition here should likely be if (!...burst mode) , right ?
> >
> > Thanks for the review!
> >
> > I was only able to test it with the DSI->ADV6535 bridge, and I'll
> > admit I don't know a lot about DSI interface since I don't have a copy
> > of the spec to read.
> >
> > Are you proposing this should be:
> >
> >   if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && dsi->lanes > 1) {
> >
> > I just want to make sure I understand what you're requesting.
>
> Yes, exactly this.

Do you think it should also include checks for
MIPI_DSI_MODE_VIDEO_NO_HFP, MIPI_DSI_MODE_VIDEO_NO_HBP or
MIPI_DSI_MODE_VIDEO_NO_HSA?

It seems like if any of these are set, we should skip this rounding stuff.

adam

Marek Vasut April 22, 2024, 7:43 p.m. UTC | #6

On 4/22/24 3:04 PM, Adam Ford wrote:
> On Mon, Apr 22, 2024 at 8:01 AM Marek Vasut <[e-mail]> wrote:
>>
>> On 4/22/24 2:09 PM, Adam Ford wrote:
>>> On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut <[e-mail]> wrote:
>>>>
>>>> On 2/12/24 12:09 AM, Adam Ford wrote:
>>>>> When using video sync pulses, the HFP, HBP, and HSA are divided between
>>>>> the available lanes if there is more than one lane.  For certain
>>>>> timings and lane configurations, the HFP may not be evenly divisible.
>>>>> If the HFP is rounded down, it ends up being too small which can cause
>>>>> some monitors to not sync properly. In these instances, adjust htotal
>>>>> and hsync to round the HFP up, and recalculate the htotal.
>>>>>
>>>>> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
>>>>> Signed-off-by: Adam Ford <[e-mail]>
>>>>> ---
>>>>> V2:  No changes
>>>>>
>>>>> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
>>>>> index 8476650c477c..52939211fe93 100644
>>>>> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
>>>>> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
>>>>> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>>>>>                 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>>>>>         }
>>>>>
>>>>> +     /*
>>>>> +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
>>>>> +      * the available lanes if there is more than one lane.  For certain
>>>>> +      * timings and lane configurations, the HFP may not be evenly divisible.
>>>>> +      * If the HFP is rounded down, it ends up being too small which can cause
>>>>> +      * some monitors to not sync properly. In these instances, adjust htotal
>>>>> +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
>>>>> +      * and error, it appears that the HBP and HSA do not appearto need the same
>>>>> +      * correction that HFP does.
>>>>> +      */
>>>>> +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
>>>>
>>>> Does this also apply to mode with sync events (I suspect it does), so
>>>> the condition here should likely be if (!...burst mode) , right ?
>>>
>>> Thanks for the review!
>>>
>>> I was only able to test it with the DSI->ADV6535 bridge, and I'll
>>> admit I don't know a lot about DSI interface since I don't have a copy
>>> of the spec to read.
>>>
>>> Are you proposing this should be:
>>>
>>>    if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && dsi->lanes > 1) {
>>>
>>> I just want to make sure I understand what you're requesting.
>>
>> Yes, exactly this.
> 
> Do you think it should also include checks for
> MIPI_DSI_MODE_VIDEO_NO_HFP, MIPI_DSI_MODE_VIDEO_NO_HBP or
> MIPI_DSI_MODE_VIDEO_NO_HSA?
> 
> It seems like if any of these are set, we should skip this rounding stuff.

Now that you ask this question, shouldn't this actually apply 
unconditionally , no matter which mode is in use ?

Marek Szyprowski April 25, 2024, 9:18 a.m. UTC | #7

On 12.02.2024 00:09, Adam Ford wrote:
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane.  For certain
> timings and lane configurations, the HFP may not be evenly divisible.
> If the HFP is rounded down, it ends up being too small which can cause
> some monitors to not sync properly. In these instances, adjust htotal
> and hsync to round the HFP up, and recalculate the htotal.
>
> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> Signed-off-by: Adam Ford <[e-mail]>

Tested-by: Marek Szyprowski <[e-mail]>

> ---
> V2:  No changes
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 8476650c477c..52939211fe93 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>   		adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>   	}
>   
> +	/*
> +	 * When using video sync pulses, the HFP, HBP, and HSA are divided between
> +	 * the available lanes if there is more than one lane.  For certain
> +	 * timings and lane configurations, the HFP may not be evenly divisible.
> +	 * If the HFP is rounded down, it ends up being too small which can cause
> +	 * some monitors to not sync properly. In these instances, adjust htotal
> +	 * and hsync to round the HFP up, and recalculate the htotal. Through trial
> +	 * and error, it appears that the HBP and HSA do not appearto need the same
> +	 * correction that HFP does.
> +	 */
> +	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
> +		int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
> +		int remainder = hfp % dsi->lanes;
> +
> +		if (remainder) {
> +			adjusted_mode->hsync_start += remainder;
> +			adjusted_mode->hsync_end   += remainder;
> +			adjusted_mode->htotal      += remainder;
> +		}
> +	}
> +
>   	return 0;
>   }
>   

Best regards

Adam Ford April 25, 2024, 8:30 p.m. UTC | #8

On Thu, Apr 25, 2024 at 4:19 AM Marek Szyprowski
<[e-mail]> wrote:
>
> On 12.02.2024 00:09, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane.  For certain
> > timings and lane configurations, the HFP may not be evenly divisible.
> > If the HFP is rounded down, it ends up being too small which can cause
> > some monitors to not sync properly. In these instances, adjust htotal
> > and hsync to round the HFP up, and recalculate the htotal.
> >
> > Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
> > Signed-off-by: Adam Ford <[e-mail]>
>
> Tested-by: Marek Szyprowski <[e-mail]>

Thank you very much for testing!

>
> > ---
> > V2:  No changes
> >
> > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> > index 8476650c477c..52939211fe93 100644
> > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
> >               adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> >       }
> >
> > +     /*
> > +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
> > +      * the available lanes if there is more than one lane.  For certain
> > +      * timings and lane configurations, the HFP may not be evenly divisible.
> > +      * If the HFP is rounded down, it ends up being too small which can cause
> > +      * some monitors to not sync properly. In these instances, adjust htotal
> > +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
> > +      * and error, it appears that the HBP and HSA do not appearto need the same
> > +      * correction that HFP does.
> > +      */
> > +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {

Frieder  &  Marek S,

Marek V is proposing we eliminate the check against the flags and do
it unconditionally.  If I send you both a different patch, would you
be willing to try them on your platforms?  I don't want to risk
breaking a board.
I used the check above from the NXP downstream kernel, so it felt
safe, but I am not as familiar with the different DSI modes, so I am
not sure what the impact would be if this read:

 if (dsi->lanes > 1) {

Does anyone else have an opinion on this?
> > +             int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
> > +             int remainder = hfp % dsi->lanes;
> > +
> > +             if (remainder) {
> > +                     adjusted_mode->hsync_start += remainder;
> > +                     adjusted_mode->hsync_end   += remainder;
> > +                     adjusted_mode->htotal      += remainder;
> > +             }
> > +     }
> > +
> >       return 0;
> >   }
> >
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>

Marek Szyprowski April 26, 2024, 5:28 a.m. UTC | #9

On 25.04.2024 22:30, Adam Ford wrote:
> On Thu, Apr 25, 2024 at 4:19 AM Marek Szyprowski
> <[e-mail]> wrote:
>> On 12.02.2024 00:09, Adam Ford wrote:
>>> When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> the available lanes if there is more than one lane.  For certain
>>> timings and lane configurations, the HFP may not be evenly divisible.
>>> If the HFP is rounded down, it ends up being too small which can cause
>>> some monitors to not sync properly. In these instances, adjust htotal
>>> and hsync to round the HFP up, and recalculate the htotal.
>>>
>>> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
>>> Signed-off-by: Adam Ford <[e-mail]>
>> Tested-by: Marek Szyprowski <[e-mail]>
> Thank you very much for testing!
>
>>> ---
>>> V2:  No changes
>>>
>>> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> index 8476650c477c..52939211fe93 100644
>>> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
>>> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>>>                adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>>>        }
>>>
>>> +     /*
>>> +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> +      * the available lanes if there is more than one lane.  For certain
>>> +      * timings and lane configurations, the HFP may not be evenly divisible.
>>> +      * If the HFP is rounded down, it ends up being too small which can cause
>>> +      * some monitors to not sync properly. In these instances, adjust htotal
>>> +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
>>> +      * and error, it appears that the HBP and HSA do not appearto need the same
>>> +      * correction that HFP does.
>>> +      */
>>> +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
> Frieder  &  Marek S,
>
> Marek V is proposing we eliminate the check against the flags and do
> it unconditionally.  If I send you both a different patch, would you
> be willing to try them on your platforms?  I don't want to risk
> breaking a board.

I'm fine with testing it. I also have some additional spare boards to 
replace the broken one, but so far none was bricked by my weird testing 
activities.

> I used the check above from the NXP downstream kernel, so it felt
> safe, but I am not as familiar with the different DSI modes, so I am
> not sure what the impact would be if this read:
>
>   if (dsi->lanes > 1) {
>
> Does anyone else have an opinion on this?
>>> +             int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
>>> +             int remainder = hfp % dsi->lanes;
>>> +
>>> +             if (remainder) {
>>> +                     adjusted_mode->hsync_start += remainder;
>>> +                     adjusted_mode->hsync_end   += remainder;
>>> +                     adjusted_mode->htotal      += remainder;
>>> +             }
>>> +     }
>>> +
>>>        return 0;
>>>    }

Best regards

Frieder Schrempf May 7, 2024, 8:40 a.m. UTC | #10

On 25.04.24 22:30, Adam Ford wrote:
> On Thu, Apr 25, 2024 at 4:19 AM Marek Szyprowski
> <[e-mail]> wrote:
>>
>> On 12.02.2024 00:09, Adam Ford wrote:
>>> When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> the available lanes if there is more than one lane.  For certain
>>> timings and lane configurations, the HFP may not be evenly divisible.
>>> If the HFP is rounded down, it ends up being too small which can cause
>>> some monitors to not sync properly. In these instances, adjust htotal
>>> and hsync to round the HFP up, and recalculate the htotal.
>>>
>>> Tested-by: Frieder Schrempf <[e-mail]> # Kontron BL i.MX8MM with HDMI monitor
>>> Signed-off-by: Adam Ford <[e-mail]>
>>
>> Tested-by: Marek Szyprowski <[e-mail]>
> 
> Thank you very much for testing!
> 
>>
>>> ---
>>> V2:  No changes
>>>
>>> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> index 8476650c477c..52939211fe93 100644
>>> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
>>> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
>>> @@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
>>>               adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>>>       }
>>>
>>> +     /*
>>> +      * When using video sync pulses, the HFP, HBP, and HSA are divided between
>>> +      * the available lanes if there is more than one lane.  For certain
>>> +      * timings and lane configurations, the HFP may not be evenly divisible.
>>> +      * If the HFP is rounded down, it ends up being too small which can cause
>>> +      * some monitors to not sync properly. In these instances, adjust htotal
>>> +      * and hsync to round the HFP up, and recalculate the htotal. Through trial
>>> +      * and error, it appears that the HBP and HSA do not appearto need the same
>>> +      * correction that HFP does.
>>> +      */
>>> +     if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
> 
> Frieder  &  Marek S,
> 
> Marek V is proposing we eliminate the check against the flags and do
> it unconditionally.  If I send you both a different patch, would you
> be willing to try them on your platforms?  I don't want to risk
> breaking a board.
> I used the check above from the NXP downstream kernel, so it felt
> safe, but I am not as familiar with the different DSI modes, so I am
> not sure what the impact would be if this read:
> 
>  if (dsi->lanes > 1) {
> 
> Does anyone else have an opinion on this?

My test only covers hardware with the ADV7535 which sets
MIPI_DSI_MODE_VIDEO_SYNC_PULSE. Doing the test without the check for
this flag won't make any difference in this case and it's therefore not
worth repeating the test.

Patch

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 8476650c477c..52939211fe93 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1606,6 +1606,27 @@  static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
 		adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 	}
 
+	/*
+	 * When using video sync pulses, the HFP, HBP, and HSA are divided between
+	 * the available lanes if there is more than one lane.  For certain
+	 * timings and lane configurations, the HFP may not be evenly divisible.
+	 * If the HFP is rounded down, it ends up being too small which can cause
+	 * some monitors to not sync properly. In these instances, adjust htotal
+	 * and hsync to round the HFP up, and recalculate the htotal. Through trial
+	 * and error, it appears that the HBP and HSA do not appearto need the same
+	 * correction that HFP does.
+	 */
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
+		int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
+		int remainder = hfp % dsi->lanes;
+
+		if (remainder) {
+			adjusted_mode->hsync_start += remainder;
+			adjusted_mode->hsync_end   += remainder;
+			adjusted_mode->htotal      += remainder;
+		}
+	}
+
 	return 0;
 }