diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 093084a48daa..3109c6651f1c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -312,7 +312,7 @@ static struct clk_mgr_funcs rv1_clk_funcs = {
 };
 
 static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = {
-	.set_dispclk = rv1_vbios_smu_set_dispclk,
+	.set_dispclk = rv1_clk_mgr_vbios_smu_set_dispclk,
 	.set_dprefclk = dce112_set_dprefclk
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 89b79dd39628..7823186250d3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -83,7 +83,7 @@ static const struct IP_BASE MP1_BASE  = { { { { 0x00016000, 0, 0, 0, 0 } },
  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
  * won't work with REG_WAIT.
  */
-static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+static uint32_t rv1_clk_mgr_vbios_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
 {
 	uint32_t res_val = VBIOSSMC_Status_BUSY;
 
@@ -101,7 +101,7 @@ static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsi
 	return res_val;
 }
 
-static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
+static int rv1_clk_mgr_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 		unsigned int msg_id, unsigned int param)
 {
 	uint32_t result;
@@ -115,7 +115,7 @@ static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	/* Trigger the message transaction by writing the message ID */
 	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
 
-	result = rv1_smu_wait_for_response(clk_mgr, 10, 1000);
+	result = rv1_clk_mgr_vbios_smu_wait_for_response(clk_mgr, 10, 1000);
 
 	ASSERT(result == VBIOSSMC_Result_OK);
 
@@ -123,14 +123,14 @@ static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	return REG_READ(MP1_SMN_C2PMSG_83);
 }
 
-int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+int rv1_clk_mgr_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
 {
 	int actual_dispclk_set_mhz = -1;
 	struct dc *dc = clk_mgr->base.ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 
 	/*  Unit of SMU msg parameter is Mhz */
-	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+	actual_dispclk_set_mhz = rv1_clk_mgr_vbios_smu_send_msg_with_param(
 			clk_mgr,
 			VBIOSSMC_MSG_SetDispclkFreq,
 			khz_to_mhz_ceil(requested_dispclk_khz));
@@ -144,11 +144,11 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di
 	return actual_dispclk_set_mhz * 1000;
 }
 
-int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
+int rv1_clk_mgr_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 {
 	int actual_dprefclk_set_mhz = -1;
 
-	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+	actual_dprefclk_set_mhz = rv1_clk_mgr_vbios_smu_send_msg_with_param(
 			clk_mgr,
 			VBIOSSMC_MSG_SetDprefclkFreq,
 			khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h
index 083cb3158859..d6d50cd3755d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h
@@ -26,7 +26,7 @@
 #ifndef DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_
 #define DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_
 
-int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
-int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
+int rv1_clk_mgr_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
+int rv1_clk_mgr_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
 
 #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
