| Message ID | 20240318203925.2837689-3-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] drm/bridge: analogix_dp: properly handle zero sized AUX transactions | expand |
On Mon, Mar 18, 2024 at 9:39 PM Lucas Stach <l.stach@pengutronix.de> wrote: > > Take a early return from the clock recovery training when the sink reports > CR_DONE for all lanes. There is no point in trying to adjust the link > parameters further. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > .../drm/bridge/analogix/analogix_dp_core.c | 58 +++++++++---------- > 1 file changed, 29 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 300385db7502..98454f0af90e 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -410,11 +410,6 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) > if (retval < 0) > return retval; > > - retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, > - adjust_request, 2); > - if (retval < 0) > - return retval; > - > if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { > /* set training pattern 2 for EQ */ > analogix_dp_set_training_pattern(dp, TRAINING_PTN2); > @@ -427,30 +422,35 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) > > dev_dbg(dp->dev, "Link Training Clock Recovery success\n"); > dp->link_train.lt_state = EQUALIZER_TRAINING; > - } else { > - for (lane = 0; lane < lane_count; lane++) { > - training_lane = analogix_dp_get_lane_link_training( > - dp, lane); > - voltage_swing = analogix_dp_get_adjust_request_voltage( > - adjust_request, lane); > - pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( > - adjust_request, lane); > - > - if (DPCD_VOLTAGE_SWING_GET(training_lane) == > - voltage_swing && > - DPCD_PRE_EMPHASIS_GET(training_lane) == > - pre_emphasis) > - dp->link_train.cr_loop[lane]++; > - > - if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || > - voltage_swing == VOLTAGE_LEVEL_3 || > - pre_emphasis == PRE_EMPHASIS_LEVEL_3) { > - dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", > - dp->link_train.cr_loop[lane], > - voltage_swing, pre_emphasis); > - analogix_dp_reduce_link_rate(dp); > - return -EIO; > - } > + > + return 0; > + } > + > + retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, > + adjust_request, 2); > + if (retval < 0) > + return retval; > + > + for (lane = 0; lane < lane_count; lane++) { > + training_lane = analogix_dp_get_lane_link_training( > + dp, lane); > + voltage_swing = analogix_dp_get_adjust_request_voltage( > + adjust_request, lane); > + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( > + adjust_request, lane); > + checkpatch --strict is throwing some warnings. Could these be fixed? -:67: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #67: FILE: drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:435: + training_lane = analogix_dp_get_lane_link_training( -:69: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #69: FILE: drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:437: + voltage_swing = analogix_dp_get_adjust_request_voltage( -:71: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #71: FILE: drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:439: + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( > + if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && > + DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) > + dp->link_train.cr_loop[lane]++; > + > + if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || > + voltage_swing == VOLTAGE_LEVEL_3 || > + pre_emphasis == PRE_EMPHASIS_LEVEL_3) { > + dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", > + dp->link_train.cr_loop[lane], > + voltage_swing, pre_emphasis); > + analogix_dp_reduce_link_rate(dp); > + return -EIO; > } > } > > -- > 2.39.2 > With the above corrected or checked, feel free to add my r-b. Reviewed-by: Robert Foss <rfoss@kernel.org>
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 300385db7502..98454f0af90e 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -410,11 +410,6 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) if (retval < 0) return retval; - retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, - adjust_request, 2); - if (retval < 0) - return retval; - if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ analogix_dp_set_training_pattern(dp, TRAINING_PTN2); @@ -427,30 +422,35 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) dev_dbg(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; - } else { - for (lane = 0; lane < lane_count; lane++) { - training_lane = analogix_dp_get_lane_link_training( - dp, lane); - voltage_swing = analogix_dp_get_adjust_request_voltage( - adjust_request, lane); - pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( - adjust_request, lane); - - if (DPCD_VOLTAGE_SWING_GET(training_lane) == - voltage_swing && - DPCD_PRE_EMPHASIS_GET(training_lane) == - pre_emphasis) - dp->link_train.cr_loop[lane]++; - - if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || - voltage_swing == VOLTAGE_LEVEL_3 || - pre_emphasis == PRE_EMPHASIS_LEVEL_3) { - dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", - dp->link_train.cr_loop[lane], - voltage_swing, pre_emphasis); - analogix_dp_reduce_link_rate(dp); - return -EIO; - } + + return 0; + } + + retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, + adjust_request, 2); + if (retval < 0) + return retval; + + for (lane = 0; lane < lane_count; lane++) { + training_lane = analogix_dp_get_lane_link_training( + dp, lane); + voltage_swing = analogix_dp_get_adjust_request_voltage( + adjust_request, lane); + pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( + adjust_request, lane); + + if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && + DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) + dp->link_train.cr_loop[lane]++; + + if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || + voltage_swing == VOLTAGE_LEVEL_3 || + pre_emphasis == PRE_EMPHASIS_LEVEL_3) { + dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", + dp->link_train.cr_loop[lane], + voltage_swing, pre_emphasis); + analogix_dp_reduce_link_rate(dp); + return -EIO; } }
Take a early return from the clock recovery training when the sink reports CR_DONE for all lanes. There is no point in trying to adjust the link parameters further. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- .../drm/bridge/analogix/analogix_dp_core.c | 58 +++++++++---------- 1 file changed, 29 insertions(+), 29 deletions(-)