| Message ID | 20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-4-78ae3ee9a697@somainline.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Initial fixes for DUALPIPE (+DSC) topology | expand |
On Wed, 17 Apr 2024 at 02:57, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > Just like the active interface and writeback block in ctl_intf_cfg_v1(), > and later the rest of the blocks in followup active-CTL fixes or > reworks, multiple calls to this function should enable additional DSC > blocks instead of overwriting the blocks that are enabled. > > This pattern is observed in an active-CTL scenario since DPU 5.0.0 where > for example bonded-DSI uses a single CTL to drive multiple INTFs, and > each encoder calls this function individually with the INTF (hence the > pre-existing update instead of overwrite of this bitmask) and DSC blocks > it wishes to be enabled, and expects them to be OR'd into the bitmask. > > The reverse already exists in reset_intf_cfg_v1() where only specified > DSC blocks are removed out of the CTL_DSC_ACTIVE bitmask (same for all > other blocks and ACTIVE bitmasks), leaving the rest enabled. > > Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index a06f69d0b257..2e50049f2f85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -545,6 +545,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, { struct dpu_hw_blk_reg_map *c = &ctx->hw; u32 intf_active = 0; + u32 dsc_active = 0; u32 wb_active = 0; u32 mode_sel = 0; @@ -560,6 +561,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); + dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); if (cfg->intf) intf_active |= BIT(cfg->intf - INTF_0); @@ -567,17 +569,18 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->wb) wb_active |= BIT(cfg->wb - WB_0); + if (cfg->dsc) + dsc_active |= cfg->dsc; + DPU_REG_WRITE(c, CTL_TOP, mode_sel); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); - if (cfg->dsc) - DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); - if (cfg->cdm) DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); }
Just like the active interface and writeback block in ctl_intf_cfg_v1(), and later the rest of the blocks in followup active-CTL fixes or reworks, multiple calls to this function should enable additional DSC blocks instead of overwriting the blocks that are enabled. This pattern is observed in an active-CTL scenario since DPU 5.0.0 where for example bonded-DSI uses a single CTL to drive multiple INTFs, and each encoder calls this function individually with the INTF (hence the pre-existing update instead of overwrite of this bitmask) and DSC blocks it wishes to be enabled, and expects them to be OR'd into the bitmask. The reverse already exists in reset_intf_cfg_v1() where only specified DSC blocks are removed out of the CTL_DSC_ACTIVE bitmask (same for all other blocks and ACTIVE bitmasks), leaving the rest enabled. Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)