| Message ID | 20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-7-78ae3ee9a697@somainline.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Initial fixes for DUALPIPE (+DSC) topology | expand |
On Wed, Apr 17, 2024 at 01:57:47AM +0200, Marijn Suijten wrote: > All other functions in dpu_hw_intf name the "self" parameter `intf`, > except dpu_hw_intf_setup_timing_engine() and the recently added > dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency. I really have mixed feelings towards such patches. On one hand it improves readability, on the other hand, it's just a name, it has no specific value. Still: Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 965692ef7892..34d0c4e04d27 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -96,11 +96,11 @@ > #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) > > > -static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > +static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_timing_params *p, > const struct dpu_format *fmt) > { > - struct dpu_hw_blk_reg_map *c = &ctx->hw; > + struct dpu_hw_blk_reg_map *c = &intf->hw; > u32 hsync_period, vsync_period; > u32 display_v_start, display_v_end; > u32 hsync_start_x, hsync_end_x; > @@ -118,7 +118,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > /* read interface_cfg */ > intf_cfg = DPU_REG_READ(c, INTF_CONFIG); > > - if (ctx->cap->type == INTF_DP) > + if (intf->cap->type == INTF_DP) > dp_intf = true; > > hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + > @@ -223,7 +223,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); > DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); > DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); > - if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { > + if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { > /* > * DATA_HCTL_EN controls data timing which can be different from > * video timing. It is recommended to enable it for all cases, except > @@ -518,10 +518,10 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, > > } > > -static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, > +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf, > struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) > { > - u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); > + u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2); > > if (cmd_mode_cfg->data_compress) > intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; > @@ -529,7 +529,7 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, > if (cmd_mode_cfg->wide_bus_en) > intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; > > - DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); > + DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); > } > > struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, > > -- > 2.44.0 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 965692ef7892..34d0c4e04d27 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -96,11 +96,11 @@ #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) -static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, +static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, const struct dpu_format *fmt) { - struct dpu_hw_blk_reg_map *c = &ctx->hw; + struct dpu_hw_blk_reg_map *c = &intf->hw; u32 hsync_period, vsync_period; u32 display_v_start, display_v_end; u32 hsync_start_x, hsync_end_x; @@ -118,7 +118,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, /* read interface_cfg */ intf_cfg = DPU_REG_READ(c, INTF_CONFIG); - if (ctx->cap->type == INTF_DP) + if (intf->cap->type == INTF_DP) dp_intf = true; hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + @@ -223,7 +223,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); - if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { + if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { /* * DATA_HCTL_EN controls data timing which can be different from * video timing. It is recommended to enable it for all cases, except @@ -518,10 +518,10 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, } -static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf, struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) { - u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); + u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2); if (cmd_mode_cfg->data_compress) intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; @@ -529,7 +529,7 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, if (cmd_mode_cfg->wide_bus_en) intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; - DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); + DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); } struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
All other functions in dpu_hw_intf name the "self" parameter `intf`, except dpu_hw_intf_setup_timing_engine() and the recently added dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)