From patchwork Mon Apr 22 18:45:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 13638826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A75BCC16B13 for ; Mon, 22 Apr 2024 18:46:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 49D2F112CE4; Mon, 22 Apr 2024 18:46:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=linux.dev header.i=@linux.dev header.b="qc80bSKU"; dkim-atps=neutral Received: from out-186.mta0.migadu.com (out-186.mta0.migadu.com [91.218.175.186]) by gabe.freedesktop.org (Postfix) with ESMTPS id E9E58112CDE for ; Mon, 22 Apr 2024 18:46:10 +0000 (UTC) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1713811569; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QTZ82xTgAAuk6SZ5l37jmN2fdwl9tEKY985CBSSyPdM=; b=qc80bSKUrkzbSUcmyZI7jqf49uMVEy1TMq6wzvzHc5FstkiuUxCjNHBBwKpaKiQxo/KG+x /NrfNbxh0yjJHUI77oupIG9WcTxuSBbXDV4P5rmR3vSDjKjtpQoJ5Oy5VzCvOWDOmo1Pvz 3aM9feB1qq8wHuzY04tX4/WOAv94lMI= From: Sean Anderson To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , dri-devel@lists.freedesktop.org Cc: David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michal Simek , Sean Anderson Subject: [PATCH v3 05/13] drm: zynqmp_dp: Rearrange zynqmp_dp for better padding Date: Mon, 22 Apr 2024 14:45:45 -0400 Message-Id: <20240422184553.3573009-6-sean.anderson@linux.dev> In-Reply-To: <20240422184553.3573009-1-sean.anderson@linux.dev> References: <20240422184553.3573009-1-sean.anderson@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Sort the members of struct zynqmp_dp to reduce padding necessary for alignment. Signed-off-by: Sean Anderson --- (no changes since v2) Changes in v2: - New drivers/gpu/drm/xlnx/zynqmp_dp.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 8635b5673386..f1834c8e3c02 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -255,10 +255,10 @@ struct zynqmp_dp_link_config { * @fmt: format identifier string */ struct zynqmp_dp_mode { - u8 bw_code; - u8 lane_cnt; - int pclock; const char *fmt; + int pclock; + u8 bw_code; + u8 lane_cnt; }; /** @@ -295,27 +295,27 @@ struct zynqmp_dp_config { * @train_set: set of training data */ struct zynqmp_dp { + struct drm_dp_aux aux; + struct drm_bridge bridge; + struct delayed_work hpd_work; + + struct drm_bridge *next_bridge; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; - int irq; - - struct drm_bridge bridge; - struct drm_bridge *next_bridge; - - struct zynqmp_dp_config config; - struct drm_dp_aux aux; struct phy *phy[ZYNQMP_DP_MAX_LANES]; - u8 num_lanes; - struct delayed_work hpd_work; + enum drm_connector_status status; + int irq; bool enabled; - u8 dpcd[DP_RECEIVER_CAP_SIZE]; - struct zynqmp_dp_link_config link_config; struct zynqmp_dp_mode mode; + struct zynqmp_dp_link_config link_config; + struct zynqmp_dp_config config; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; + u8 num_lanes; }; static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge)