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Sun, 02 Jun 2024 14:39:54 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 03 Jun 2024 00:39:51 +0300 Subject: [PATCH v2 5/9] drm/msm/dpu: check for the plane pitch overflow MIME-Version: 1.0 Message-Id: <20240603-dpu-mode-config-width-v2-5-16af520575a6@linaro.org> References: <20240603-dpu-mode-config-width-v2-0-16af520575a6@linaro.org> In-Reply-To: <20240603-dpu-mode-config-width-v2-0-16af520575a6@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=4803hWNpcHudkouDSAWKTu5smpjA3R/H+DmuPg5Dn0I=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmXOal57sL8VMNXDeoG/fMtixB373FIQWN8gw/p Jsq7M8PeNyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlzmpQAKCRCLPIo+Aiko 1SS8B/9IvoUaga2Nmr6zLxDaPC0Pc/bQ9umyzktyaqzhu5FrXAUTstXPTkXN/Vvvm4IgHL7Oifm WcQeu9aesYxb/ZJPQ9o8vy36CGWa35+aCrBfj8HB9h/IHRsCXNKIZGdKg9TzZi4bnYOuSAnGiae roe0B46ZN0KiaM5s0ZS916amsyfzrXGBUTq5YkK6vWozKe4spG4H/JLLyrGee8y91BOfhjj5UtR dpDVLc3WUp65moHflX0M1QkiW6L/w9O/SKw8QQZ/Im24w8SS84aULi/YwCxDO1SP3DdHux9xecx 98Aj0bzISAffMSqrXlRQ6NhYl61qevbjcTGXb7aPmBYGevrW X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Check that the plane pitch doesn't overflow the maximum pitch size allowed by the hardware. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 4a910b808687..8998d1862e16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -12,6 +12,8 @@ struct dpu_hw_sspp; +#define DPU_SSPP_MAX_PITCH_SIZE 0xffff + /** * Flags */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 927fde2f1391..b5848fae14ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -791,7 +791,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); - int ret = 0, min_scale; + int i, ret = 0, min_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; @@ -865,6 +865,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return ret; } + for (i = 0; i < pstate->layout.num_planes; i++) + if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) + return -E2BIG; + fmt = msm_framebuffer_format(new_plane_state->fb); max_linewidth = pdpu->catalog->caps->max_linewidth;