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[46.135.45.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-422871ec9e6sm28201695e9.38.2024.06.12.06.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 06:53:10 -0700 (PDT) From: Tomeu Vizoso Date: Wed, 12 Jun 2024 15:52:57 +0200 Subject: [PATCH 4/9] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588s MIME-Version: 1.0 Message-Id: <20240612-6-10-rocket-v1-4-060e48eea250@tomeuvizoso.net> References: <20240612-6-10-rocket-v1-0-060e48eea250@tomeuvizoso.net> In-Reply-To: <20240612-6-10-rocket-v1-0-060e48eea250@tomeuvizoso.net> To: Joerg Roedel , Will Deacon , Robin Murphy , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Oded Gabbay , Tomeu Vizoso , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Philipp Zabel , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, Tomeu Vizoso X-Mailer: b4 0.13.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" See Chapter 36 "RKNN" from the RK3588 TRM (Part 1). This is a derivative of NVIDIA's NVDLA, but with its own front-end processor. Mostly taken from downstream. Signed-off-by: Tomeu Vizoso --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 6ac5ac8b48ab..a5d53578c8f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2665,6 +2665,59 @@ gpio4: gpio@fec50000 { #interrupt-cells = <2>; }; }; + + rknn: npu@fdab0000 { + compatible = "rockchip,rk3588-rknn", "rockchip,rknn"; + reg = <0x0 0xfdab0000 0x0 0x9000>, + <0x0 0xfdac0000 0x0 0x9000>, + <0x0 0xfdad0000 0x0 0x9000>; + interrupts = , + , + ; + interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; + clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>, + <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, + <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, + <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>; + clock-names = "clk_npu", + "aclk0", "aclk1", "aclk2", + "hclk0", "hclk1", "hclk2", + "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>, + <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2"; + power-domains = <&power RK3588_PD_NPUTOP>, + <&power RK3588_PD_NPU1>, + <&power RK3588_PD_NPU2>; + power-domain-names = "npu0", "npu1", "npu2"; + iommus = <&rknn_mmu>; + status = "disabled"; + }; + + rknn_mmu: iommu@fdab9000 { + compatible = "rockchip,rk3588-iommu"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>, + <0x0 0xfdaca000 0x0 0x100>, + <0x0 0xfdada000 0x0 0x100>; + interrupts = , + , + ; + interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu"; + clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, + <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>; + clock-names = "aclk0", "aclk1", "aclk2", + "iface0", "iface1", "iface2"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPUTOP>, + <&power RK3588_PD_NPU1>, + <&power RK3588_PD_NPU2>; + power-domain-names = "npu0", "npu1", "npu2"; + status = "disabled"; + }; }; #include "rk3588s-pinctrl.dtsi"