From patchwork Thu Jul 25 13:56:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13741978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A383AC3DA49 for ; Thu, 25 Jul 2024 14:06:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27D6010E829; Thu, 25 Jul 2024 14:06:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ov3OS/gj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 11AF410E834; Thu, 25 Jul 2024 14:06:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721916372; x=1753452372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ykvhi9CLDv624qgten1HNwsh5CZkKKRX9KCLAGda0l8=; b=Ov3OS/gjJohwy4hGumDLVh42w8gNuIGwLtFxlBSBbg7oYqjz0Si5dCYL UsASelN4FCZS6tTx35Pg5C0NlQTeLkr4PM6x9wMviQchHjsxnbsgTxKsg ICVIUHxD0GNxdpRznbK8i6WC888FklLtJKuH4qpB//p6J7rDfSOSWAKbh GiutIGhKLKHp5fl91UiNuVuAZC/RuSLn7OlC43Vg8VWtgHnUBMxlY9kPM MNaeRJlDf07DOVrZXFvwPYpzvdSY7WHXUnePTM5OKxabKxk1EP2msApHk PbmocZ6/msdlMqzYH3iV5BWKlK390KWQbsNcPC24eIw4BuHmgd5iPC12z g==; X-CSE-ConnectionGUID: aBoMVWmEQd2VnPQ5kGG/Ng== X-CSE-MsgGUID: bX17TzRzTAKUSjYdoNbCiw== X-IronPort-AV: E=McAfee;i="6700,10204,11144"; a="19504937" X-IronPort-AV: E=Sophos;i="6.09,236,1716274800"; d="scan'208";a="19504937" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2024 07:06:12 -0700 X-CSE-ConnectionGUID: w2prjSJfTQqnE2MDYMt/eA== X-CSE-MsgGUID: Ie87jppNRguJzuLI+ImUKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,236,1716274800"; d="scan'208";a="53007828" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2024 07:06:04 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 09/12] drm/i915/spi: add intel_spi_region map Date: Thu, 25 Jul 2024 16:56:54 +0300 Message-Id: <20240725135657.1061836-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725135657.1061836-1-alexander.usyskin@intel.com> References: <20240725135657.1061836-1-alexander.usyskin@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tomas Winkler Add the dGFX spi region map and convey it via auxiliary device to the spi child device. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c index 17e4c7861ef5..8dd4065551e2 100644 --- a/drivers/gpu/drm/i915/spi/intel_spi.c +++ b/drivers/gpu/drm/i915/spi/intel_spi.c @@ -11,6 +11,13 @@ #define GEN12_GUNIT_SPI_SIZE 0x80 +static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = { + [0] = { .name = "DESCRIPTOR", }, + [2] = { .name = "GSC", }, + [11] = { .name = "OptionROM", }, + [12] = { .name = "DAM", }, +}; + static void i915_spi_release_dev(struct device *dev) { } @@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv) spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; spi->bar.flags = IORESOURCE_MEM; spi->bar.desc = IORES_DESC_NONE; + spi->regions = regions; aux_dev->name = "spi"; aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |