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Mon, 30 Sep 2024 05:29:10 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8005.024; Mon, 30 Sep 2024 05:29:10 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, o.rempel@pengutronix.de, y.moog@phytec.de Subject: [PATCH 2/8] arm64: dts: imx8mp-phyboard-pollux-rdk: Add panel-timing node to panel-lvds node Date: Mon, 30 Sep 2024 13:28:57 +0800 Message-Id: <20240930052903.168881-3-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930052903.168881-1-victor.liu@nxp.com> References: <20240930052903.168881-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR06CA0015.apcprd06.prod.outlook.com (2603:1096:4:186::7) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|GV1PR04MB10536:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a323e82-e9f9-4600-aa53-08dce110d00f X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This way, 74.25MHz clock frequency specified in panel-timing node may accommodate 7-fold 519.75MHz "media_ldb" clock which is derived from 1.0395GHz "video_pll1" clock. This should suppress this LDB driver warning: [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (72400000 Hz) does not match requested LVDS clock: 506800000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support") Signed-off-by: Liu Ying --- .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 50debe821c42..20cb5363cccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { backlight = <&backlight_lvds>; power-supply = <®_vcc_3v3_sw>; + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <72>; + hback-porch = <86>; + hsync-len = <2>; + vfront-porch = <15>; + vback-porch = <21>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + }; + port { panel1_in: endpoint { remote-endpoint = <&ldb_lvds_ch1>;