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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-287ab9b5ba5sm188924fac.21.2024.10.02.19.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 19:58:39 -0700 (PDT) From: Bjorn Andersson Date: Wed, 02 Oct 2024 20:01:32 -0700 Subject: [PATCH RFT 1/2] firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID MIME-Version: 1.0 Message-Id: <20241002-adreno-smmu-aparture-v1-1-e9a63c9ccef5@oss.qualcomm.com> References: <20241002-adreno-smmu-aparture-v1-0-e9a63c9ccef5@oss.qualcomm.com> In-Reply-To: <20241002-adreno-smmu-aparture-v1-0-e9a63c9ccef5@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Bjorn Andersson X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2997; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=ECeOnqwkL9oJWvy2IoxkgjFotjTcF/KXI8WgJ2j6Ppk=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBm/gkcWIcpdn2/xdWuhuQYvPCj6vFgI+ERHLL5B uxSWZReAIaJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZv4JHBUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcUMmA//eVBu9B7Ev3OMWmjXNH9MrFelo5hICM0seNCG3VO +xJ2dGbDsRl0spsDLFrzU1Zc685JBF2nRUf49/4zzfxNRmatKgP6dl1sLrI7eop/q401e5JyXlI ia82MIwlc9RIXwXJ5qRIK7rWHcSo2jx6LebTAnz6DZibrfxKO4w/F8OI6t7N5Mml0gCncndzk3/ D5C4PHwDkPA82gmRS0RxaC/KU8snVqQVN2PeJ9o6LmqA6jGrYJtAQeqY8c1gBVHitOakiWcSctr X4MmOK0eZ/i1XmuSuX3L8c871yghyY6wIW8pxHKzcwOYC49YeKcSSNwZ4KOmMkYBbgBxInZc8Va WOBSsObLppy1VnZnWjSaVCOI2E10xJRzwfw/D1lmcHcMWiEsCJ/S0O+HB0Aj6/ZAnfNxZ9GLE/n 3b5cKMjF5aedpllWqJIPXL4CC6EdZP9iU+Ap9sR62bmmC0FsL62n0W/eslwZetwPWere3fsUSwm jf9eVvc013pwtmg4mnkos3G3GNd6EwhjImSmCbFRaMpLH36WFtbszc2LvCnMQ+NTuIusthd8JTn wUwgZ/tLBEQxZ8S47AHE4GdJmTBh7N+A7lSuBhSeeVaJbHyWkgaOGIexogqcthZLWqvtKGlf02S IR2aCKp0+2A9BHC7dLood5uZVGjvCyQRUwlpn2IuX+V4= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-ORIG-GUID: EGE3yI5Oj0xk2AdkDlpQZK8W1OV9fO3T X-Proofpoint-GUID: EGE3yI5Oj0xk2AdkDlpQZK8W1OV9fO3T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxscore=0 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2410030019 X-Mailman-Approved-At: Thu, 03 Oct 2024 07:37:11 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The QCOM_SCM_SVC_MP service provides QCOM_SCM_MP_CP_SMMU_APERTURE_ID, which is used to trigger the mapping of register banks into the SMMU context for per-processes page tables to function (in case this isn't statically setup by firmware). This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB bus error"-errors from the GPU. Introduce a function to allow the msm driver to invoke this call. Signed-off-by: Bjorn Andersson Tested-by: Konrad Dybcio # FP5 Reviewed-by: Konrad Dybcio Tested-by: Jessica Zhang # Trogdor (sc7180) --- drivers/firmware/qcom/qcom_scm.c | 19 +++++++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 1 + include/linux/firmware/qcom/qcom_scm.h | 1 + 3 files changed, 21 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 10986cb11ec0..bd633c57b6e8 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -903,6 +903,25 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) } EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg); +#define QCOM_SCM_CP_APERTURE_CONTEXT_MASK GENMASK(7, 0) + +int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_CP_SMMU_APERTURE_ID, + .arginfo = QCOM_SCM_ARGS(4), + .args[0] = 0xffff0000 | FIELD_PREP(QCOM_SCM_CP_APERTURE_CONTEXT_MASK, context_bank), + .args[1] = 0xffffffff, + .args[2] = 0xffffffff, + .args[3] = 0xffffffff, + .owner = ARM_SMCCC_OWNER_SIP + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture); + int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { struct qcom_scm_desc desc = { diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 685b8f59e7a6..e36b2f67607f 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -116,6 +116,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05 #define QCOM_SCM_MP_VIDEO_VAR 0x08 #define QCOM_SCM_MP_ASSIGN 0x16 +#define QCOM_SCM_MP_CP_SMMU_APERTURE_ID 0x1b #define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c #define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d #define QCOM_SCM_MP_SHM_BRIDGE_CREATE 0x1e diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 9f14976399ab..23ec8ee5e49f 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -85,6 +85,7 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); bool qcom_scm_restore_sec_cfg_available(void); int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); +int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank); int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);