From patchwork Tue Oct 8 22:38:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13827117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 793B8CF042B for ; Tue, 8 Oct 2024 22:39:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0788110E26A; Tue, 8 Oct 2024 22:39:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.b="Ho8P2zPG"; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42F0810E287 for ; Tue, 8 Oct 2024 22:39:01 +0000 (UTC) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 5175688F4B; Wed, 9 Oct 2024 00:38:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1728427139; bh=KJKH/WpYHcVDKhYFQkulqQ+jQNo550/ZRk57bNzhqsQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ho8P2zPGsvkWVTq6nno9yUYUNYZAeiKD0pHx3LTu8uLRqwux4wXbpbpuOsVT76RmB cgrXrgUgyHGXgbtR0HTE/BuE1osAo12f883QukUgk8HMPk5+CnZq9gKKTa8xRPpRDy aInZNMB0dcY06lGFF2xQsqjbf+nLskckktP9uBvvuefOO5Z5GAYGV/y+CnSSExcZ7Q IBRy/veAZ2/SRtNpodtdqsJoFPegju8NyeUve0ixY/Jfw6FqUT9E8P9ZeXLkQp3WYI AVtBX3chfvi5SX6zDorSDh5VbsjewK7Tnyxcejj2xfFb3gqSSseCdWVgWMm/JmEvtU mBB2Ikbv8Pk+Q== From: Marek Vasut To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Abel Vesa , Andrzej Hajda , David Airlie , Fabio Estevam , Isaac Scott , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Michael Turquette , Neil Armstrong , Peng Fan , Pengutronix Kernel Team , Robert Foss , Sascha Hauer , Shawn Guo , Simona Vetter , Stephen Boyd , Thomas Zimmermann , imx@lists.linux.dev, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] drm: bridge: ldb: Configure LDB clock in .mode_set Date: Wed, 9 Oct 2024 00:38:20 +0200 Message-ID: <20241008223846.337162-2-marex@denx.de> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241008223846.337162-1-marex@denx.de> References: <20241008223846.337162-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The LDB serializer clock operate at either x7 or x14 rate of the input LCDIFv3 scanout engine clock. Make sure the serializer clock and their upstream Video PLL are configured early in .mode_set to the x7 or x14 rate of pixel clock, before LCDIFv3 .atomic_enable is called which would configure the Video PLL to low x1 rate, which is unusable. With this patch in place, the clock tree is correctly configured. The example below is for a 71.1 MHz pixel clock panel, the LDB serializer clock is then 497.7 MHz: video_pll1_ref_sel 1 1 0 24000000 0 0 50000 video_pll1 1 1 0 497700000 0 0 50000 video_pll1_bypass 1 1 0 497700000 0 0 50000 video_pll1_out 2 2 0 497700000 0 0 50000 media_ldb 1 1 0 497700000 0 0 50000 media_ldb_root_clk 1 1 0 497700000 0 0 50000 media_disp2_pix 1 1 0 71100000 0 0 50000 media_disp2_pix_root_clk 1 1 0 71100000 0 0 50000 Signed-off-by: Marek Vasut Tested-by: Isaac Scott --- Cc: Abel Vesa Cc: Andrzej Hajda Cc: David Airlie Cc: Fabio Estevam Cc: Isaac Scott Cc: Jernej Skrabec Cc: Jonas Karlman Cc: Laurent Pinchart Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Michael Turquette Cc: Neil Armstrong Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Robert Foss Cc: Sascha Hauer Cc: Shawn Guo Cc: Simona Vetter Cc: Stephen Boyd Cc: Thomas Zimmermann Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org --- drivers/gpu/drm/bridge/fsl-ldb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 0e4bac7dd04ff..a3a31467fcc85 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -278,6 +278,16 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, return MODE_OK; } +static void fsl_ldb_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adj) +{ + struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); + unsigned long requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); + + clk_set_rate(fsl_ldb->clk, requested_link_freq); +} + static const struct drm_bridge_funcs funcs = { .attach = fsl_ldb_attach, .atomic_enable = fsl_ldb_atomic_enable, @@ -287,6 +297,7 @@ static const struct drm_bridge_funcs funcs = { .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, .atomic_reset = drm_atomic_helper_bridge_reset, .mode_valid = fsl_ldb_mode_valid, + .mode_set = fsl_ldb_mode_set, }; static int fsl_ldb_probe(struct platform_device *pdev)