From patchwork Thu Oct 17 01:21:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13839225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4406FD2F7D9 for ; Thu, 17 Oct 2024 01:21:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 171A610E77C; Thu, 17 Oct 2024 01:21:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.b="VvwMq7ug"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id A54FD10E774; Thu, 17 Oct 2024 01:21:31 +0000 (UTC) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49GDVUUC016699; Thu, 17 Oct 2024 01:21:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wlCBp7WNkEaSceMKeOgYXqObgq2ohbQi8VvgBY58bvI=; b=VvwMq7ug3bTsiOaV NOnKHFImi7DVate5YCxPR+3wEpCHn9MSl9TjohUGaOt9zCse8BhsXiFNE09BmjbO NRYK2pCh1sWLdvPvhLqLbX1zYDAcIBqNhLc6pULuTspJIcz+Dh0hBWoEnaBP3Ymy mLgYZPpadEHCcktvb2znnbPZqqtK6y3Ma2vEG3KI42uF5pRXmItFowLBxhnxV95y FKLVaqpCFBapDQ+BFWQnqe2DuAFsi6nfrXxxZDWoK0fYEBf1a1xMGX5Kz+ZrO/7x uG/ixYVkSvIvcmhT/J0XrUIxkt7uwZzQfqzxH3aBc1OAutOt7wUKZIc3/7cvMLyw e76++Q== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42a8w6jw6m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 01:21:20 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H1LJb1026856 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 01:21:19 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 16 Oct 2024 18:21:19 -0700 From: Jessica Zhang Date: Wed, 16 Oct 2024 18:21:19 -0700 Subject: [PATCH v3 13/23] drm/msm/dpu: Add CWB to msm_display_topology MIME-Version: 1.0 Message-ID: <20241016-concurrent-wb-v3-13-a33cf9b93835@quicinc.com> References: <20241016-concurrent-wb-v3-0-a33cf9b93835@quicinc.com> In-Reply-To: <20241016-concurrent-wb-v3-0-a33cf9b93835@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Simona Vetter , Simona Vetter CC: , , , , , Rob Clark , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-2a633 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729128075; l=3267; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=u1Pu54PNPCL7XNIum5pyxxJCkNJtfuelrEJnsmdK3QI=; b=9ERiP6I1Av0+sASWp9QNSJtbXb4HWlmYpe6X/v8Hub36ORnB11iv9nAiJu7y4W1tThEtZ5DgX Uqs5ONXwiecBmwJGJCdCD1XaLGaXHSYs2/XyvQ5xJpT456YjwXYT+t2 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y0DyBORbBBtVW2uBQtlFJZGA5IFF9ZXX X-Proofpoint-ORIG-GUID: y0DyBORbBBtVW2uBQtlFJZGA5IFF9ZXX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170008 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the cwb_enabled flag to msm_display topology and adjust the toplogy to account for concurrent writeback Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++++++++-- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index d53e986eee5467d78aa3b4cc2bc59a954942cdea..5af506a66d5b5cce172e66bfea85b483a8fa1c70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1176,6 +1176,8 @@ static struct msm_display_topology dpu_crtc_get_topology( dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, &crtc_state->adjusted_mode); + topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); + /* * Datapath topology selection * @@ -1187,9 +1189,16 @@ static struct msm_display_topology dpu_crtc_get_topology( * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * * Add dspps to the reservation requirements if ctm is requested + * + * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not + * enabled. This is because in cases where CWB is enabled, num_intf will + * count both the WB and real-time phys encoders. + * + * For non-DSC CWB usecases, have the num_lm be decided by the + * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. */ - if (topology.num_intf == 2) + if (topology.num_intf == 2 && !topology.cwb_enabled) topology.num_lm = 2; else if (topology.num_dsc == 2) topology.num_lm = 2; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 96c80cf9f6ad60cef9fb5fda38179b8ef4f5de4a..04df3056d75a799ad4bdc87d6a9c97acdb990323 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -371,8 +371,14 @@ static int _dpu_rm_reserve_ctls( int i = 0, j, num_ctls; bool needs_split_display; - /* each hw_intf needs its own hw_ctrl to program its control path */ - num_ctls = top->num_intf; + /* + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its + * control path. Hardcode num_ctls to 1 if CWB is enabled + */ + if (top->cwb_enabled) + num_ctls = 1; + else + num_ctls = top->num_intf; needs_split_display = _dpu_rm_needs_split_display(top); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2e28a13446366caae48ff6291d5f88db06de645e..34a378cecfe0eef45262592c9f9e8e4234f37a29 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -84,6 +85,7 @@ struct msm_display_topology { u32 num_dspp; u32 num_dsc; bool needs_cdm; + bool cwb_enabled; }; /* Commit/Event thread specific structure */