diff mbox series

[v3,15/23] drm/msm/dpu: Fail atomic_check if CWB and CDM are enabled

Message ID 20241016-concurrent-wb-v3-15-a33cf9b93835@quicinc.com (mailing list archive)
State New, archived
Headers show
Series drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ | expand

Commit Message

Jessica Zhang Oct. 17, 2024, 1:21 a.m. UTC 
We cannot support both CWB and CDM simultaneously as this would require
2 CDM blocks and currently our hardware only supports 1 CDM block at
most.

Thus return an error if both CWB and CDM are enabled.

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 118ef6c14d0c9207329b9fdbf590e392fcb87ecd..b156175c81898d5c0b5dc4692bf44fa74dffa574 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1239,6 +1239,10 @@  static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_stat
 		return 0;
 
 	topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state);
+
+	if (topology.cwb_enabled && topology.needs_cdm)
+		return -EINVAL;
+
 	ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
 			     crtc, &topology);
 	if (ret)