Message ID | 20241016-upstream-v6-v6-1-4d93a0c46de1@ite.com.tw (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/bridge: it6505: fix HDCP CTS fail items and add MCCS support | expand |
On Wed, Oct 16, 2024 at 03:54:13PM +0800, Hermes Wu via B4 Relay wrote: > From: Hermes Wu <Hermes.wu@ite.com.tw> > > The hardware AUX FIFO is 16 bytes > Change definition of AUX_FIFO_MAX_SIZE to 16 > > Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver") > Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> > --- > drivers/gpu/drm/bridge/ite-it6505.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index 7ff17aa14b01e4d9f626424e065131ae2b195c62..3272ca6951f2585f9592834869de23ac50ce41a4 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -300,7 +300,7 @@ #define MAX_CR_LEVEL 0x03 #define MAX_EQ_LEVEL 0x03 #define AUX_WAIT_TIMEOUT_MS 15 -#define AUX_FIFO_MAX_SIZE 32 +#define AUX_FIFO_MAX_SIZE 16 #define PIXEL_CLK_DELAY 1 #define PIXEL_CLK_INVERSE 0 #define ADJUST_PHASE_THRESHOLD 80000