From patchwork Wed Oct 16 03:25:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 13837648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E675D206A3 for ; Wed, 16 Oct 2024 03:25:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B6A4910E666; Wed, 16 Oct 2024 03:25:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EXMvGJPV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA87D10E652; Wed, 16 Oct 2024 03:25:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729049101; x=1760585101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Rhq0od1gt2wuUofhIwYc5H7ttqJYEzdoRIRFxCTNX8=; b=EXMvGJPVDZiwbv2TKUGn2oARgfLsCdZ5ADd9bO3TLhwxTxMdk0+JFqZr YUZsik8uvZ6CAgra46ZPDXF9oOIzHkaIt2MTwoFCKTsqwHMIJHztRKJet dbu2U0WcBjPDgKD1F8ESw6+Ahweyus5R9RUdaEN4qsq5IbX3kgO35ZWjU /6z9vY2ofS0akfZ1zh6n280Mq4+xeZKEiAVTpjdyTc0/MKOowlH7ZlbOI I47AqqWxgEbXaTEexOZ4Eh9sFp94gQVLX/xzJGIBDwtvppsavRKNvGsq4 1rixJsz65gCDzOiEj9q8MZnKSqmbZk0VyahDgey5NPLn3/H0UV+8TnQPy A==; X-CSE-ConnectionGUID: wkz4ncrrSDy2VshvvG5DdA== X-CSE-MsgGUID: xZPPg0ETQF62yn4qzQEVsA== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="39056457" X-IronPort-AV: E=Sophos;i="6.11,206,1725346800"; d="scan'208";a="39056457" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2024 20:24:59 -0700 X-CSE-ConnectionGUID: 9VTIUnhhSP2StqYDpKMfHw== X-CSE-MsgGUID: SyISU9A9T4udhJtI0mtNow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,206,1725346800"; d="scan'208";a="78930274" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2024 20:24:58 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: apopple@nvidia.com, airlied@gmail.com, christian.koenig@amd.com, thomas.hellstrom@linux.intel.com, simona.vetter@ffwll.ch, felix.kuehling@amd.com, dakr@kernel.org Subject: [PATCH v2 22/29] drm/xe: Add Xe SVM devmem_release vfunc Date: Tue, 15 Oct 2024 20:25:11 -0700 Message-Id: <20241016032518.539495-23-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241016032518.539495-1-matthew.brost@intel.com> References: <20241016032518.539495-1-matthew.brost@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement with a simple BO put. v2: - Use new drm_gpusvm_devmem_ops Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_svm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index 19fcb8f71791..976b4ce15db4 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -5,6 +5,7 @@ #include "drm_gpusvm.h" +#include "xe_bo.h" #include "xe_gt_tlb_invalidation.h" #include "xe_migrate.h" #include "xe_pt.h" @@ -419,6 +420,11 @@ static struct xe_bo *to_xe_bo(struct drm_gpusvm_devmem *devmem_allocation) return container_of(devmem_allocation, struct xe_bo, devmem_allocation); } +static void xe_svm_devmem_release(struct drm_gpusvm_devmem *devmem_allocation) +{ + xe_bo_put(to_xe_bo(devmem_allocation)); +} + static u64 block_offset_to_pfn(struct xe_mem_region *mr, u64 offset) { return PHYS_PFN(offset + mr->hpa_base); @@ -454,6 +460,7 @@ static int xe_svm_populate_devmem_pfn(struct drm_gpusvm_devmem *devmem_allocatio __maybe_unused static const struct drm_gpusvm_devmem_ops gpusvm_devmem_ops = { + .devmem_release = xe_svm_devmem_release, .populate_devmem_pfn = xe_svm_populate_devmem_pfn, .copy_to_devmem = xe_svm_copy_to_devmem, .copy_to_ram = xe_svm_copy_to_ram,