From patchwork Thu Nov 21 04:25:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 13881616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7FACD75BB0 for ; Thu, 21 Nov 2024 04:26:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9320510E85A; Thu, 21 Nov 2024 04:26:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="lJ7Fk6GJ"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A3B710E857 for ; Thu, 21 Nov 2024 04:26:10 +0000 (UTC) X-UUID: b985490aa7c011ef99858b75a2457dd9-20241121 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mJDZ8TbEOg8kfWuALOz+YShjGUyzgs27hJEVqgGGWq4=; b=lJ7Fk6GJHltgO5mTmTR7V8w82jcMT+ncF2fNdF0gODkrxb4fHG1+Oxwewpy5y6gwEzyeQxPxtzuMWrVsfWK3zSwQbYWL+QR8kZQMCuBTFgPf3EJSfWYgTwG53Mu/ysY4i2pc281E4FWX/SqErO60Nc2wpaXkvudeN2FJsxxHGqc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.44, REQID:7072b010-d679-496a-83b1-da887196d3be, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:464815b, CLOUDID:8e35d6fe-58af-4a77-b036-41f515d81476, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:-3,IP :nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: b985490aa7c011ef99858b75a2457dd9-20241121 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1235469517; Thu, 21 Nov 2024 12:26:05 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 21 Nov 2024 12:26:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 21 Nov 2024 12:26:04 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Mauro Carvalho Chehab CC: David Airlie , Simona Vetter , Moudy Ho , , , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH 5/8] soc: mediatek: mtk-cmdq: Add mminfra_offset compatibility for DRAM address Date: Thu, 21 Nov 2024 12:25:59 +0800 Message-ID: <20241121042602.32730-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241121042602.32730-1-jason-jh.lin@mediatek.com> References: <20241121042602.32730-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since GCE has been moved to mminfra in MT8196, all transactions from mminfra to DRAM will have their addresses adjusted by subtracting a mminfra offset. This information should be handled inside the CMDQ driver, allowing CMDQ users to call CMDQ APIs as usual. Therefore, CMDQ driver needs to use the mbox API to get the mminfra_offset value of the SoC, and then add it to the DRAM address when generating instructions to ensure GCE accesses the correct DRAM address. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 43 +++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index ffdf3cecf6fe..bd2aa9152afc 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -222,6 +222,9 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base, u16 offset, u32 if (cmdq_subsys_is_valid(cl->chan, subsys)) { err = cmdq_pkt_append_command(pkt, inst); } else { + if (cmdq_addr_need_offset(cl->chan, pa_base)) + pa_base += cmdq_get_offset_pa(cl->chan); + err = cmdq_pkt_assign(pkt, 0, CMDQ_ADDR_HIGH(pa_base)); if (err < 0) return err; @@ -255,12 +258,16 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base, } err = cmdq_pkt_write(pkt, subsys, pa_base, offset_mask, value); } else { + if (cmdq_addr_need_offset(cl->chan, pa_base)) + pa_base += cmdq_get_offset_pa(cl->chan); + err = cmdq_pkt_assign(pkt, 0, CMDQ_ADDR_HIGH(pa_base)); if (err < 0) return err; err = cmdq_pkt_write_s_mask_value(pkt, 0, CMDQ_ADDR_LOW(offset), value, mask); } + return err; } EXPORT_SYMBOL(cmdq_pkt_write_mask); @@ -347,10 +354,22 @@ EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value); int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr) { + struct cmdq_client *cl = (struct cmdq_client *)pkt->cl; const u16 high_addr_reg_idx = CMDQ_THR_SPR_IDX0; const u16 value_reg_idx = CMDQ_THR_SPR_IDX1; int ret; + if (!cl) { + pr_err("%s %d: pkt->cl is NULL!\n", __func__, __LINE__); + return -EINVAL; + } + + if (cmdq_addr_need_offset(cl->chan, src_addr)) + src_addr += cmdq_get_offset_pa(cl->chan); + + if (cmdq_addr_need_offset(cl->chan, dst_addr)) + dst_addr += cmdq_get_offset_pa(cl->chan); + /* read the value of src_addr into high_addr_reg_idx */ ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr)); if (ret < 0) @@ -450,6 +469,9 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base, } if (!cmdq_subsys_is_valid(cl->chan, subsys)) { + if (cmdq_addr_need_offset(cl->chan, pa_base)) + pa_base += cmdq_get_offset_pa(cl->chan); + err = cmdq_pkt_assign(pkt, CMDQ_POLL_ADDR_GPR, pa_base); if (err < 0) return err; @@ -480,10 +502,19 @@ EXPORT_SYMBOL(cmdq_pkt_poll_mask); int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask) { + struct cmdq_client *cl = (struct cmdq_client *)pkt->cl; struct cmdq_instruction inst = { {0} }; u8 use_mask = 0; int ret; + if (!cl) { + pr_err("%s %d: pkt->cl is NULL!\n", __func__, __LINE__); + return -EINVAL; + } + + if (cmdq_addr_need_offset(cl->chan, addr)) + addr += cmdq_get_offset_pa(cl->chan); + /* * Append an MASK instruction to set the mask for following POLL instruction * which enables use_mask bit. @@ -561,11 +592,21 @@ EXPORT_SYMBOL(cmdq_pkt_assign); int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { + struct cmdq_client *cl = (struct cmdq_client *)pkt->cl; struct cmdq_instruction inst = { .op = CMDQ_CODE_JUMP, .offset = CMDQ_JUMP_ABSOLUTE, - .value = addr >> shift_pa }; + + if (!cl) { + pr_err("%s %d: pkt->cl is NULL!\n", __func__, __LINE__); + return -EINVAL; + } + + if (cmdq_addr_need_offset(cl->chan, addr)) + addr += cmdq_get_offset_pa(cl->chan); + + inst.value = addr >> shift_pa; return cmdq_pkt_append_command(pkt, inst); } EXPORT_SYMBOL(cmdq_pkt_jump_abs);