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Mon, 2 Dec 2024 02:58:52 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%6]) with mapi id 15.20.8207.017; Mon, 2 Dec 2024 02:58:52 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: p.zabel@pengutronix.de, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, glx@linutronix.de, vkoul@kernel.org, kishon@kernel.org, aisheng.dong@nxp.com, agx@sigxcpu.org, francesco@dolcini.it, frank.li@nxp.com, dmitry.baryshkov@linaro.org, u.kleine-koenig@baylibre.com Subject: [DO NOT MERGE PATCH v5 19/19] arm64: dts: imx8qxp-mek: Add MX8-DLVDS-LCD1 display module support Date: Mon, 2 Dec 2024 10:56:35 +0800 Message-Id: <20241202025635.1274467-20-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202025635.1274467-1-victor.liu@nxp.com> References: <20241202025635.1274467-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR06CA0005.apcprd06.prod.outlook.com (2603:1096:4:186::12) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|DBBPR04MB7643:EE_ X-MS-Office365-Filtering-Correlation-Id: bd10f0b1-ba36-4b5b-6ce6-08dd127d4102 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Add an overlay to support the LCD panel on i.MX8qxp MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd and even pixels to the panel respectively. Signed-off-by: Liu Ying --- v5: * No change. v4: * No change. v3: * No change. v2: * New patch. (Francesco) arch/arm64/boot/dts/freescale/Makefile | 4 + .../imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso | 183 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 30 +++ 3 files changed, 217 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 42e6482a31cb..a22476e81cc7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -254,6 +254,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb + +imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd-dtbs += imx8qxp-mek.dtb imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso new file mode 100644 index 000000000000..7ddd90e68754 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-mx8-dlvds-lcd1-lvds0-odd.dtso @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + panel-lvds0 { + compatible = "koe,tx26d202vm0bwa"; + backlight = <&backlight_lvds1>; + power-supply = <®_vcc_per_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_lvds0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + }; +}; + +&backlight_lvds1 { + status = "okay"; +}; + +&dc0_framegen0 { + assigned-clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <0>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>; + assigned-clock-rates = <940320000>; +}; + +&dc0_pixel_link0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + status = "okay"; + }; + }; +}; + +&dc0_pc { + status = "okay"; + + channel@0 { + status = "okay"; + }; +}; + +&mipi_lvds_0_ldb { + #address-cells = <1>; + #size-cells = <0>; + fsl,companion-ldb = <&mipi_lvds_1_ldb>; + status = "okay"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds0_in>; + }; + }; + }; +}; + +&mipi_lvds_0_phy { + status = "okay"; +}; + +&mipi_lvds_0_pxl2dpi { + fsl,companion-pxl2dpi = <&mipi_lvds_1_pxl2dpi>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + status = "okay"; + }; + }; + + port@1 { + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + status = "okay"; + }; + }; + }; +}; + +&mipi_lvds_1_ldb { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_lvds_1_phy { + status = "okay"; +}; + +&mipi_lvds_1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + status = "okay"; +}; + +&mipi_lvds_1_pxl2dpi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link0: endpoint@1 { + status = "okay"; + }; + }; + + port@1 { + reg = <1>; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1: endpoint@1 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index c7b4015c7bf7..cb999be00c22 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -21,6 +21,16 @@ chosen { stdout-path = &lpuart0; }; + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&mipi_lvds_1_pwm 0 100000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + power-supply = <®_vcc_12v0>; + status = "disabled"; + }; + imx8x_cm4: imx8x-cm4 { compatible = "fsl,imx8qxp-cm4"; mbox-names = "tx", "rx", "rxdb"; @@ -58,6 +68,20 @@ dsp_vdev0buffer: memory@94300000 { }; }; + reg_vcc_12v0: regulator-vcc-12v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_vcc_per_3v3: regulator-vcc-per-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_PER_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -785,6 +809,12 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; + pinctrl_pwm_mipi_lvds1: mipilvds1pwmgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 + >; + }; + pinctrl_pcieb: pcieagrp { fsl,pins = < IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021