From patchwork Sat Dec 7 16:15:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13898324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BA45E7717E for ; Sat, 7 Dec 2024 16:18:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF1D810E431; Sat, 7 Dec 2024 16:18:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JXftTQnB"; dkim-atps=neutral Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC1CD10E428; Sat, 7 Dec 2024 16:18:15 +0000 (UTC) Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-725c049fbd7so1396629b3a.3; Sat, 07 Dec 2024 08:18:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733588295; x=1734193095; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fIPC3wN4RB22AtTIYzOFUGMqESGQ71MfkPRGJ75Lpqo=; b=JXftTQnBu8KvWX4DEZzrX/0AnG8LulQwOvU9up5/y6FXq7AGc5OOJcow4yqZaUde/n dxf5lL+1ebewmLbEyrBsUoKdxZjCSsBKFE6aPeqC8nFPwWYneZ+pBv9RoxoVLL7uowsv pcrRiM3qHYeVc4PvUMoHlcS5GtiwXPjITwNUSVh0ybCxntkOHWOACsW2kthsmFKC6zxw fTArUOrVd+EDs3QUEasWyjyoM7Tsl9XRAs7q6EYq3MLi9Fi/fsTNm/D1T1Zc/pzUmbkN qZo001exIJnxyXsyHcmphj44LXOC0OJfmlIZk8TSfX+DB0QfOZfKVQJy6+/tfBOBDxL5 KZAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733588295; x=1734193095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fIPC3wN4RB22AtTIYzOFUGMqESGQ71MfkPRGJ75Lpqo=; b=eNSSbhVz/0YhSP4Dquc8om/OmNxTepV//uP/qX8Aqf7usg109AqcyC32uUga9gCWFN +okHdT6GRG7puco9ll4JZZP0TTW2qa7qMknBEHd9cZyMkNLee8KEIp/Ji+XIOo4NRPTG nx9Fl/N9zJmuYrrXKu3XGokz7ux+6qEcksBE4iHdiIIXv+NrqpyeKuNVq254T/dK9Jqi xyqZb3eg/5Kd2pRGoCkYVQmaoNP+JuZfBnaWguFbwNfoTX3H8oB0jJOJz3TgAnGXZTRd vtJo8cC8btOvtazs6CjlZPkOtpMJEtpP9ZoWhOVtKRAaHh7qmkmTk3SHQ/aSuDe95LOI Tbjg== X-Gm-Message-State: AOJu0YxwLKmLKb8LTBKrUe4ScUSYXBD+XdxZ3GfML7YEIjzf3rnf97+A gaJveY2iDk6nf8J7kWzyB0G4u+692AX3caC/2F1TmZFEQ96ueCypeprbfA== X-Gm-Gg: ASbGncs3tbYf1Bmx1j358NJnYaoIf06HmW4w6XXxdP2mstEKcQFO1VE1oUkkuCLqQYp odW7PO13d3cmjrT79srB3ARTbWDdxbvHndbXTeE3lzOE9Z4Z56SoM5HHE485PEZ+DbvVYaKCa94 Ye1Q7Guwrazpntkq/M/k9x4c3IlHgYsA8Xebd3OBhbvSt2e4lldQqlrobbwyaT830jHqDNPuCW/ V4xvQHintwhr6/F6PrGMqizFcydtkUqwoNXYrdv2Am7XK11FVcjYsDjXwVAd5F2ne9BXVsPjYEK tnxnxR6q X-Google-Smtp-Source: AGHT+IFWDLy7ds21MKUC3Cq7AuB7/7Sndz2UK9nF/2GtDakUzwnVagIsycjTJ4PrKiaKXWcXS6yeyQ== X-Received: by 2002:a05:6a20:9185:b0:1dc:7907:6d67 with SMTP id adf61e73a8af0-1e18717aed4mr13758619637.40.1733588294811; Sat, 07 Dec 2024 08:18:14 -0800 (PST) Received: from localhost (c-73-37-105-206.hsd1.or.comcast.net. [73.37.105.206]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7fd1568eadbsm4764479a12.12.2024.12.07.08.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Dec 2024 08:18:14 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Connor Abbott , Akhil P Oommen , Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , linux-kernel@vger.kernel.org (open list) Subject: [RFC 21/24] drm/msm: Add PRR support Date: Sat, 7 Dec 2024 08:15:21 -0800 Message-ID: <20241207161651.410556-22-robdclark@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241207161651.410556-1-robdclark@gmail.com> References: <20241207161651.410556-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark Add PRR (Partial Resident Region) is a bypass address which make GPU writes go to /dev/null and reads return zero. This is used to implement vulkan sparse residency. To support PRR/NULL mappings, we allocate a page to reserve a physical address which we know will not be used as part of a GEM object, and configure the SMMU to use this address for PRR/NULL mappings. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++++ drivers/gpu/drm/msm/msm_iommu.c | 62 ++++++++++++++++++++++++- include/uapi/drm/msm_drm.h | 2 + 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 90848852ee50..140b4e54bc96 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -308,6 +308,13 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, return 0; } +static bool +adreno_smmu_has_prr(struct msm_gpu *gpu) +{ + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev); + return adreno_smmu && adreno_smmu->set_prr_addr; +} + int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, uint32_t param, uint64_t *value, uint32_t *len) { @@ -392,6 +399,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, case MSM_PARAM_UCHE_TRAP_BASE: *value = adreno_gpu->uche_trap_base; return 0; + case MSM_PARAM_HAS_PRR: + *value = adreno_smmu_has_prr(gpu); + return 0; default: return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param); } diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 41cb629e25f3..bb65be95f7db 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -13,6 +13,7 @@ struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain; atomic_t pagetables; + struct page *prr_page; }; #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) @@ -112,6 +113,36 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, return (size == 0) ? 0 : -EINVAL; } +static int msm_iommu_pagetable_map_prr(struct msm_mmu *mmu, u64 iova, size_t len, int prot) +{ + struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); + struct io_pgtable_ops *ops = pagetable->pgtbl_ops; + struct msm_iommu *iommu = to_msm_iommu(pagetable->parent); + phys_addr_t phys = page_to_phys(iommu->prr_page); + u64 addr = iova; + + while (len) { + size_t mapped = 0; + size_t size = PAGE_SIZE; + int ret; + + ret = ops->map_pages(ops, addr, phys, size, 1, prot, GFP_KERNEL, &mapped); + + /* map_pages could fail after mapping some of the pages, + * so update the counters before error handling. + */ + addr += mapped; + len -= mapped; + + if (ret) { + msm_iommu_pagetable_unmap(mmu, iova, addr - iova); + return -EINVAL; + } + } + + return 0; +} + static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova, struct sg_table *sgt, size_t off, size_t len, int prot) @@ -122,6 +153,9 @@ static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova, u64 addr = iova; unsigned int i; + if (!sgt) + return msm_iommu_pagetable_map_prr(mmu, iova, len, prot); + for_each_sgtable_sg(sgt, sg, i) { size_t size = sg->length; phys_addr_t phys = sg_phys(sg); @@ -177,9 +211,16 @@ static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) * If this is the last attached pagetable for the parent, * disable TTBR0 in the arm-smmu driver */ - if (atomic_dec_return(&iommu->pagetables) == 0) + if (atomic_dec_return(&iommu->pagetables) == 0) { adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL); + if (adreno_smmu->set_prr_bit) { + adreno_smmu->set_prr_bit(adreno_smmu->cookie, false); + __free_page(iommu->prr_page); + iommu->prr_page = NULL; + } + } + free_io_pgtable_ops(pagetable->pgtbl_ops); kfree(pagetable); } @@ -314,6 +355,25 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) kfree(pagetable); return ERR_PTR(ret); } + + BUG_ON(iommu->prr_page); + if (adreno_smmu->set_prr_bit) { + /* + * We need a zero'd page for two reasons: + * + * 1) Reserve a known physical address to use when + * mapping NULL / sparsely resident regions + * 2) Read back zero + * + * It appears the hw drops writes to the PRR region + * on the floor, but reads actually return whatever + * is in the PRR page. + */ + iommu->prr_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + adreno_smmu->set_prr_addr(adreno_smmu->cookie, + page_to_phys(iommu->prr_page)); + adreno_smmu->set_prr_bit(adreno_smmu->cookie, true); + } } /* Needed later for TLB flush */ diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index a7e48ee1dd95..48bc0374e2ae 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -115,6 +115,8 @@ struct drm_msm_timespec { * ioctl will throw -EPIPE. */ #define MSM_PARAM_EN_VM_BIND 0x15 /* WO, once */ +/* PRR (Partially Resident Region) is required for sparse residency: */ +#define MSM_PARAM_HAS_PRR 0x16 /* RO */ /* For backwards compat. The original support for preemption was based on * a single ring per priority level so # of priority levels equals the #