From patchwork Mon Dec 9 16:25:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13900027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3149E77187 for ; Mon, 9 Dec 2024 16:35:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3081410E503; Mon, 9 Dec 2024 16:35:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gZ3KGRqL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FA2510E4DB; Mon, 9 Dec 2024 16:35:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733762108; x=1765298108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VTpPi6Zz+oo/0Ag5LfX7yPCuVjN5rKQuHCq69vPDlLQ=; b=gZ3KGRqLpFdWQVevhMDCEcmFiRiRUMWTnpyxWuTjFJ1+2/KgkIcv5UYt ceZUDQrY11aiaJqJphYl1JfeniSHub7C5FwxJCzRueOyZR5nEl5AQK6UW WC9kDot0CkmJcsf7tEPnSgenom81aI9c8zP6qMlkYMq2pWC7yXx8ioWwJ xKMxwVbLtfFEJaHaOSt+5OWEA9JJR9cOqD/kfx3IbHdxgz99+EjZuxTRi ijusZUqTtsV9hGt6oiQefjhoRoQ9K7NZB71F+R1Y3K2wjDvNRv7X1vDqA GhGfGAGCjrd3DKdgTp9/QWCYVVaaeIu8lmdxzFpD1Iik9GAxJ4FvYPzs/ A==; X-CSE-ConnectionGUID: lS9oDuocRgCJYl57APpbsw== X-CSE-MsgGUID: wI97721xTNeEPnrsfdQRAA== X-IronPort-AV: E=McAfee;i="6700,10204,11281"; a="56551695" X-IronPort-AV: E=Sophos;i="6.12,219,1728975600"; d="scan'208";a="56551695" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2024 08:35:07 -0800 X-CSE-ConnectionGUID: 5s5i7MrkRYSBvTmgfzNMpQ== X-CSE-MsgGUID: jU1lXGN6SCC2TnZGvxqVpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,219,1728975600"; d="scan'208";a="118371775" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa002.fm.intel.com with ESMTP; 09 Dec 2024 08:35:06 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv2 10/10] drm/i915/histogram: Enable pipe dithering Date: Mon, 9 Dec 2024 21:55:04 +0530 Message-Id: <20241209162504.2146697-11-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241209162504.2146697-1-arun.r.murthy@intel.com> References: <20241209162504.2146697-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable pipe dithering while enabling histogram to overcome some atrifacts seen on the screen. Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_histogram.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index d503d0f0a5ee..545376ae365b 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -29,6 +29,13 @@ struct intel_histogram { u32 bin_data[HISTOGRAM_BIN_COUNT]; }; +static void intel_histogram_enable_dithering(struct intel_display *display, + enum pipe pipe) +{ + intel_de_rmw(display, PIPE_MISC(pipe), PIPE_MISC_DITHER_ENABLE, + PIPE_MISC_DITHER_ENABLE); +} + static void set_bin_index_0(struct intel_display *display, enum pipe pipe) { if (DISPLAY_VER(display) >= 20) @@ -207,6 +214,9 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc) if (histogram->enable) return 0; + /* Pipe Dithering should be enabled with histogram */ + intel_histogram_enable_dithering(display, pipe); + /* enable histogram, clear DPST_BIN reg and select TC function */ if (DISPLAY_VER(display) >= 20) intel_de_rmw(display, DPST_CTL(pipe),