@@ -287,22 +287,22 @@ static const struct dpu_dsc_cfg sm8650_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x6,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x6,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x6,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x6,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
@@ -272,12 +272,12 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
},
};
@@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
},
};
@@ -273,12 +273,12 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
@@ -287,12 +287,12 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
},
};
@@ -286,12 +286,12 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
@@ -281,12 +281,12 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
},
};
@@ -281,12 +281,12 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] = {
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .have_native_42x = 1,
.sblk = &dsc_sblk_1,
},
};
@@ -128,16 +128,6 @@ enum {
DPU_VBIF_MAX
};
-/**
- * DSC sub-blocks/features
- * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
- * @DPU_DSC_MAX
- */
-enum {
- DPU_DSC_NATIVE_42x_EN = 0x1,
- DPU_DSC_MAX
-};
-
/**
* MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
* @name: string name for debug purposes
@@ -474,10 +464,12 @@ struct dpu_merge_3d_cfg {
* @len: length of hardware block
* @features bit mask identifying sub-blocks/features
* @sblk: sub-blocks information
+ * @have_native_42x: Supports NATIVE_422 and NATIVE_420 encoding
*/
struct dpu_dsc_cfg {
DPU_HW_BLK_INFO;
const struct dpu_dsc_sub_blks *sblk;
+ unsigned long have_native_42x : 1;
};
/**
@@ -62,7 +62,7 @@ static int _dsc_calc_output_buf_max_addr(struct dpu_hw_dsc *hw_dsc, int num_soft
{
int max_addr = 2400 / num_softslice;
- if (hw_dsc->caps->features & BIT(DPU_DSC_NATIVE_42x_EN))
+ if (hw_dsc->caps->have_native_42x)
max_addr /= 2;
return max_addr - 1;
Continue cleanup of the feature flags and replace the last remaining LM feature with a bitfield flag, simplifying corresponding data structures and access. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 2 +- 10 files changed, 20 insertions(+), 28 deletions(-)