From patchwork Tue Dec 17 23:33:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 13912685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 332F5E7718D for ; Tue, 17 Dec 2024 23:33:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 712DE10EAA8; Tue, 17 Dec 2024 23:33:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U0Y2kb9R"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D68110E845; Tue, 17 Dec 2024 23:33:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734478392; x=1766014392; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q/0Dr6KxdST7Wb2xg4gcSZtD+jDVYk9Zjkx0L1rp9Ec=; b=U0Y2kb9RP4b0Bj3gQbHwCcMrud6+jeb0fC4uMSVLuxl8pVTDtF14WtK2 ohwqwZRAZMTGCgiI4dSb15EEswd06IC2f0/mAR2MZJrYlYg8r1lFILHFa IUeLbmrGDw9nYo0GXCb6n+UlvVFLFj9ybd837YxtMdIxQab04oX1wMEqM ns/QIQYMThEygKUCuAZ1tKndaiGO6QbFF74+rZmVRDIyYiPvocTXbZNZh pw74pZDCPmkSd4ClT390HHVGoWqCOki1K6zounH7I8Vr1z7NM1HJ1Q5zx mubFkd4kXtri/biaaPLhEY50LIKFcw2b20ZLhc30ga7BUYc0rt8PaGWFc A==; X-CSE-ConnectionGUID: vmDWfJAlQP+uEizOFP9g2Q== X-CSE-MsgGUID: jaGqk/WFQP6XZl/RFQBedA== X-IronPort-AV: E=McAfee;i="6700,10204,11289"; a="22517426" X-IronPort-AV: E=Sophos;i="6.12,243,1728975600"; d="scan'208";a="22517426" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 15:33:11 -0800 X-CSE-ConnectionGUID: 4uHHfG2BQqC91Kxlrq+SqQ== X-CSE-MsgGUID: 6L/i3mkBQaCPBkipsunSyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="102273447" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 15:33:11 -0800 From: Matthew Brost To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: apopple@nvidia.com, airlied@gmail.com, christian.koenig@amd.com, thomas.hellstrom@linux.intel.com, simona.vetter@ffwll.ch, felix.kuehling@amd.com, dakr@kernel.org Subject: [PATCH v3 17/30] drm/xe: Enable CPU address mirror uAPI Date: Tue, 17 Dec 2024 15:33:35 -0800 Message-Id: <20241217233348.3519726-18-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217233348.3519726-1-matthew.brost@intel.com> References: <20241217233348.3519726-1-matthew.brost@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Support for CPU address mirror bindings in SRAM fully in place, enable the implementation. v3: - s/system allocator/CPU address mirror (Thomas) Signed-off-by: Matthew Brost Reviewed-by: Thomas Hellström --- drivers/gpu/drm/xe/xe_svm.c | 10 ++++++++++ drivers/gpu/drm/xe/xe_vm.c | 6 ------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index 8237b534a65b..3cbf29732249 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -428,6 +428,16 @@ int xe_svm_handle_pagefault(struct xe_vm *vm, struct xe_vma *vma, return err; } +/** + * xe_svm_has_mapping() - SVM has mappings + * @vm: The VM. + * @start: Start address. + * @end: End address. + * + * Check if an address range has SVM mappings. + * + * Return: True is address range has a SVM mapping, False otherwise + */ bool xe_svm_has_mapping(struct xe_vm *vm, u64 start, u64 end) { return drm_gpusvm_has_mapping(&vm->svm.gpusvm, start, end); diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 613a68498a24..12cbb140404d 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3020,12 +3020,6 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm, u16 pat_index = (*bind_ops)[i].pat_index; u16 coh_mode; - /* FIXME: Disabling CPU address mirror for now */ - if (XE_IOCTL_DBG(xe, is_cpu_addr_mirror)) { - err = -EOPNOTSUPP; - goto free_bind_ops; - } - if (XE_IOCTL_DBG(xe, is_cpu_addr_mirror && !xe_vm_in_fault_mode(vm))) { err = -EINVAL;