| Message ID | 20250207-topic-sm8x50-mdss-interconnect-bindings-fix-v2-1-f712b8df6020@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: display: qcom,sm8[56]50-mdss: only document the mdp0-mem interconnect path | expand |
On Fri, 7 Feb 2025 at 16:02, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > The mdp1-mem is not supported on the SM8550 SoCs, so only support a single > mdp0-mem interconnect entry. v2 went too fast. Please add cpu-cfg instead. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > .../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml > index 1ea50a2c7c8e9f420125ad30a80b4ebd05c9367a..9631fe11c152449f3dfa0b8f8f53feeba721c950 100644 > --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml > @@ -30,10 +30,10 @@ properties: > maxItems: 1 > > interconnects: > - maxItems: 2 > + maxItems: 1 > > interconnect-names: > - maxItems: 2 > + maxItems: 1 > > patternProperties: > "^display-controller@[0-9a-f]+$": > @@ -91,9 +91,8 @@ examples: > reg = <0x0ae00000 0x1000>; > reg-names = "mdss"; > > - interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, > - <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; > - interconnect-names = "mdp0-mem", "mdp1-mem"; > + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem"; > > resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > > > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml index 1ea50a2c7c8e9f420125ad30a80b4ebd05c9367a..9631fe11c152449f3dfa0b8f8f53feeba721c950 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -30,10 +30,10 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + maxItems: 1 interconnect-names: - maxItems: 2 + maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": @@ -91,9 +91,8 @@ examples: reg = <0x0ae00000 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, - <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
The mdp1-mem is not supported on the SM8550 SoCs, so only support a single mdp0-mem interconnect entry. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- .../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)