From patchwork Mon Feb 17 16:41:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13978303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CD20C021A9 for ; Mon, 17 Feb 2025 16:42:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8C1610E578; Mon, 17 Feb 2025 16:42:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="OJbGOtKq"; dkim-atps=neutral Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6DF910E55F for ; Mon, 17 Feb 2025 16:41:58 +0000 (UTC) Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-5dbe706f94fso670981a12.2 for ; Mon, 17 Feb 2025 08:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739810517; x=1740415317; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VJrYVmgp1aq41qu2TkRbEXVfothnDoOWiCK5wVOL2Vg=; b=OJbGOtKq8r4Sapoes7Ev8q2FG75j+A9K2q8hDrfHCmwEWrQU6A8xUnl1V9yDkXcUC/ iqMEFh1gV8MBu8dv5bbQkRuaZ/kYuBSCAVwjZWOP0zdMxyNtn3E4YDfX1x9QyFnmdphH UJFC4NoJWhyzRcX+Q+aD0YIDvmPhkcWLcWEBcvsd9aZN7INLVpYcrxS6Gll2EciubdKM hy50b9MRG4G+ut3wwP6z6AhusgZQmNnzI0hDRmw+kt/yUiRoxPv3LbM0BnxBSfkBx5HS IZ9BPLFwccRxhQNP/UqTofEpqusl8KhxA2mMsfLugrQkDvG6Hl+jg/RFS8jj6uSdFUpt +1UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739810517; x=1740415317; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VJrYVmgp1aq41qu2TkRbEXVfothnDoOWiCK5wVOL2Vg=; b=APlVzyIe3VKjYRhnZmr79j/v0mG0RKArQ4gdK0LOhvd5F0qeXDcJYYOZ21i35NaWqe uyV0qU69Wz32QYD94hSS2fCpsoPH16schXWzI2GUCva0EDmhbF09DAtHRfw2i+zxcsXE kT8zpI1muc4cFvNpxC48W7UnfR9fv8eRcmGPlGiUjQ7d2w8AoVTahgp3LIiWHWxynWcc xUfOiPbacSVQtZY9d2tb+QcYVhs8PyusHqmzr2D2LKEuVU9LSFdhQDewEC0KvTnMEsyc PWukuf2W/AFLWGb+vpAEOmZb+O9twiXSB23TGjTIVrg5/ayH7x/N42VOCDV28b/H4dM+ DQRw== X-Forwarded-Encrypted: i=1; AJvYcCWo+dbmgublHptaBMoPg5unVuY8pdzkVZG+oyMiYqf0DNDiFuLtynpepuoUyT2nEbN2/neQ60rtzCk=@lists.freedesktop.org X-Gm-Message-State: AOJu0YyY8H3Sir/kt3ccHOUP7ZsHKdj9D6cROCEr0Ly2v98U81f2yMeN CS0H9XTBtAvKU5PvZNiwi1rEtoC6NElW1YrnjEKjIInknfLi3VAPyHQLmVHKawU= X-Gm-Gg: ASbGncuXcefx7vgLgSXzI9Qhqo6nt297A1It7G0jIDuPx+ZlveTFzcZy4LgoX+1Y2tv gO/7ARYDFp+wLaYflZiX6CX+5k2G24/5cYM1UzeTBrQAJigBlH7xLLKPnubNDn6+AlRxbgs8Kcv VN8UMyqD7W1quJ1uGj+KeoKr43rzuttuGatMSwvoSpgNlKpjinMj0aXZMCoy72iba5/VbJFe809 WPnqdbl5L89orSJCaBGlptRHbdw7JlnbLR9BIG9zGRPBk1IBrZ9kJktQ+jJ+zdwLx6bBRp2CBVt Fn+hfWlrIVrsykn+Wg9X5baX3QGEj8c= X-Google-Smtp-Source: AGHT+IFNxYxTpIkHTpnq3dLgMOrAmMAJapI/BVIfp/kHf/I/VXombYH8IEQ/Pi9svRCvnCKuSKuJNQ== X-Received: by 2002:a17:907:1c21:b0:aa5:a60:ad6a with SMTP id a640c23a62f3a-abb70d51d61mr422961466b.8.1739810517116; Mon, 17 Feb 2025 08:41:57 -0800 (PST) Received: from [127.0.1.1] ([178.197.206.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbac781b78sm82647966b.60.2025.02.17.08.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Feb 2025 08:41:56 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 17 Feb 2025 17:41:28 +0100 Subject: [PATCH v2 07/16] dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750 MIME-Version: 1.0 Message-Id: <20250217-b4-sm8750-display-v2-7-d201dcdda6a4@linaro.org> References: <20250217-b4-sm8750-display-v2-0-d201dcdda6a4@linaro.org> In-Reply-To: <20250217-b4-sm8750-display-v2-0-d201dcdda6a4@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16118; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=gV9/ZNQKNVCER9lMGYxfkuxKDiNH46wKVuhbuG5aEYk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBns2a92FvUXS7c3v7iStHJj+ipWwdx1E/xcaZ+a 9ZagHtk8OiJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ7NmvQAKCRDBN2bmhouD 12puD/9elkf2gjZQqCFzjWw+eLL3yKIaPDhCTVZqsVY5Lk434xqtOMWfpQ/1fD72ocLWoNeRCox evkiPQK941Io4Yvaf8cVHX/LyG3Ne3haIqltntieIIyWag8X+Y3Y/z1wghoC9C6I6N6jI7rWiWC Z0s4CWauTf9fmsUW+HFztqhhI+st5gNCcepDoR4+LfqZd4QmrduhTXa+7N9IHuh116xn7JBFVvK CU9kReiOQS0RXFgXfP/EZiiVmanU7FHBHVfAsO8OmndKvU9+6Phj0L+CWNzhZ/vT4P0sa5K9FQB rzJt4NoVS32Sw5h71Z9Zl9RyZXVLvYhJrB4oy1WRqa1H3A/w58Qq5p4LsrqGuQOEYyrZ9YNrmDe H09jQIb48MJ3Tr9vm0/o5uPZ7lrRwEhSb4IF3hjmFv5QNJt/ajN2uwvWXi2gF2tZHkjCdxcnVQ4 LX29Kr5XoMNtn5SvmbXfn28X+Tp0IwnaEVbi6upXdiNCoeh5LdvKfnUf9D4EshflbJ/rrR5HnrN 41VlWx3W13ol+/7yqreN7Z1UavuYGUPYnvR7PbDapQ4cKf0RowEK8O/HheHE+f5KHD2w0RYCCuY YHtHzkZ458J1nZEa5hLQnTSDF1QBk+UPzAIbeF36f8uoRAKdRptM1EG0Q4BVnbvhH2DcoICke+J lNgYFydoSwc3Lfg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation with two revisions up of the IP block comparing to SM8650. Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 460 +++++++++++++++++++++ 1 file changed, 460 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..cfa21b0d081338f1b94779594798f86284ba0677 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -0,0 +1,460 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Display MDSS + +maintainers: + - Krzysztof Kozlowski + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8750-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + items: + - const: qcom,sm8750-dp + - const: qcom,sm8650-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + items: + - const: qcom,sm8750-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sm8750-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>; + + resets = <&disp_cc_mdss_core_bcr>; + + power-domains = <&mdss_gdsc>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8750-dpu"; + reg = <0x0ae01000 0x93000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + vdda-supply = <&vreg_l3g_1p2>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + vdds-supply = <&vreg_l3i_0p88>; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + dsi@ae96000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&disp_cc_mdss_byte1_clk>, + <&disp_cc_mdss_byte1_intf_clk>, + <&disp_cc_mdss_pclk1_clk>, + <&disp_cc_mdss_esc1_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&disp_cc_esync1_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte1_clk_src>, + <&disp_cc_mdss_pclk1_clk_src>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + displayport-controller@af54000 { + compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg = <0xaf54000 0x104>, + <0xaf54200 0xc0>, + <0xaf55000 0x770>, + <0xaf56000 0x9c>, + <0xaf57000 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_dptx0_aux_clk>, + <&disp_cc_mdss_dptx0_link_clk>, + <&disp_cc_mdss_dptx0_link_intf_clk>, + <&disp_cc_mdss_dptx0_pixel0_clk>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, + <&disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + }; + };