From patchwork Wed Feb 19 09:20:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jay Liu X-Patchwork-Id: 13983135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD0CDC021B1 for ; Wed, 19 Feb 2025 23:48:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B953E10E8B9; Wed, 19 Feb 2025 23:48:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="CQv6I+/5"; dkim-atps=neutral Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4A5510E799 for ; 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Wed, 19 Feb 2025 17:21:16 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Wed, 19 Feb 2025 17:21:15 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Wed, 19 Feb 2025 17:21:14 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , , , Jay Liu Subject: [PATCH 7/7] dt-bindings: display: mediatek: tdshp: Add support for MT8196 Date: Wed, 19 Feb 2025 17:20:40 +0800 Message-ID: <20250219092040.11227-8-jay.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20250219092040.11227-1-jay.liu@mediatek.com> References: <20250219092040.11227-1-jay.liu@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 19 Feb 2025 23:48:37 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../display/mediatek/mediatek,tdshp.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml new file mode 100644 index 000000000000..5ed7bdd53d0e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display clarity correction + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display clarity correction, namely TDSHP, provides a + operation used to adjust sharpness in display system. + TDSHP device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8196-disp-tdshp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + + soc { + #address-cells = <2>; + #size-cells = <2>; + + tdshp@321e0000 { + compatible = "mediatek,mt8196-disp-tdshp"; + reg = <0 0x321e0000 0 0x1000>; + clocks = <&dispsys_config_clk 107>; + }; + };