diff mbox series

[6/7] drm/msm/dpu: allocate single CTL for DPU >= 5.0

Message ID 20250220-dpu-active-ctl-v1-6-71ca67a564f8@linaro.org (mailing list archive)
State New
Headers show
Series drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms | expand

Commit Message

Dmitry Baryshkov Feb. 20, 2025, 10:26 a.m. UTC 
Unlike previous generation, since DPU 5.0 it is possible to use just one
CTL to handle all INTF and WB blocks for a single output. And one has to
use single CTL to support bonded DSI config. Allocate single CTL for
these DPU versions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +++++++++++++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 ++
 2 files changed, 15 insertions(+), 4 deletions(-)

Comments

Marijn Suijten Feb. 20, 2025, 11:34 p.m. UTC | #1 
On 2025-02-20 12:26:23, Dmitry Baryshkov wrote:
> Unlike previous generation, since DPU 5.0 it is possible to use just one
> CTL to handle all INTF and WB blocks for a single output. And one has to
> use single CTL to support bonded DSI config. Allocate single CTL for
> these DPU versions.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +++++++++++++----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 ++
>  2 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 5baf9df702b84b74ba00e703ad3cc12afb0e94a4..4dbc9bc7eb4f151f83055220665ee5fd238ae7ba 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -53,6 +53,8 @@ int dpu_rm_init(struct drm_device *dev,
>  	/* Clear, setup lists */
>  	memset(rm, 0, sizeof(*rm));
>  
> +	rm->has_legacy_ctls = (cat->mdss_ver->core_major_ver < 5);
> +
>  	/* Interrogate HW catalog and create tracking items for hw blocks */
>  	for (i = 0; i < cat->mixer_count; i++) {
>  		struct dpu_hw_mixer *hw;
> @@ -381,10 +383,16 @@ static int _dpu_rm_reserve_ctls(
>  	int i = 0, j, num_ctls;
>  	bool needs_split_display;
>  
> -	/* each hw_intf needs its own hw_ctrl to program its control path */
> -	num_ctls = top->num_intf;
> +	if (rm->has_legacy_ctls) {
> +		/* each hw_intf needs its own hw_ctrl to program its control path */
> +		num_ctls = top->num_intf;
>  
> -	needs_split_display = _dpu_rm_needs_split_display(top);
> +		needs_split_display = _dpu_rm_needs_split_display(top);
> +	} else {
> +		/* use single CTL */
> +		num_ctls = 1;
> +		needs_split_display = false;
> +	}
>  
>  	for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
>  		const struct dpu_hw_ctl *ctl;
> @@ -402,7 +410,8 @@ static int _dpu_rm_reserve_ctls(
>  
>  		DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
>  
> -		if (needs_split_display != has_split_display)
> +		if (rm->has_legacy_ctls &&
> +		    needs_split_display != has_split_display)

I deduced a long time ago that the check for rm->has_legacy_ctls is not needed.

needs_split_display is always false on DPU >= 5, and neither of those SoCs has
DPU_CTRL_SPLIT_DISPLAY which means false != false is false, and this condition
never triggers on active CTLs even without checking has_legacy_ctls.

Other than that, this is all successfully tested and:

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

>  			continue;
>  
>  		ctl_idx[i] = j;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 99bd594ee0d1995eca5a1f661b15e24fdf6acf39..130f753c36338544e84a305b266c3b47fa028d84 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -24,6 +24,7 @@ struct dpu_global_state;
>   * @dspp_blks: array of dspp hardware resources
>   * @hw_sspp: array of sspp hardware resources
>   * @cdm_blk: cdm hardware resource
> + * @has_legacy_ctls: DPU uses pre-ACTIVE CTL blocks.
>   */
>  struct dpu_rm {
>  	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> @@ -37,6 +38,7 @@ struct dpu_rm {
>  	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>  	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
>  	struct dpu_hw_blk *cdm_blk;
> +	bool has_legacy_ctls;
>  };
>  
>  struct dpu_rm_sspp_requirements {
> 
> -- 
> 2.39.5
>
Dmitry Baryshkov Feb. 20, 2025, 11:58 p.m. UTC | #2 
On Fri, Feb 21, 2025 at 12:34:12AM +0100, Marijn Suijten wrote:
> On 2025-02-20 12:26:23, Dmitry Baryshkov wrote:
> > Unlike previous generation, since DPU 5.0 it is possible to use just one
> > CTL to handle all INTF and WB blocks for a single output. And one has to
> > use single CTL to support bonded DSI config. Allocate single CTL for
> > these DPU versions.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +++++++++++++----
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 ++
> >  2 files changed, 15 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index 5baf9df702b84b74ba00e703ad3cc12afb0e94a4..4dbc9bc7eb4f151f83055220665ee5fd238ae7ba 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > @@ -53,6 +53,8 @@ int dpu_rm_init(struct drm_device *dev,
> >  	/* Clear, setup lists */
> >  	memset(rm, 0, sizeof(*rm));
> >  
> > +	rm->has_legacy_ctls = (cat->mdss_ver->core_major_ver < 5);
> > +
> >  	/* Interrogate HW catalog and create tracking items for hw blocks */
> >  	for (i = 0; i < cat->mixer_count; i++) {
> >  		struct dpu_hw_mixer *hw;
> > @@ -381,10 +383,16 @@ static int _dpu_rm_reserve_ctls(
> >  	int i = 0, j, num_ctls;
> >  	bool needs_split_display;
> >  
> > -	/* each hw_intf needs its own hw_ctrl to program its control path */
> > -	num_ctls = top->num_intf;
> > +	if (rm->has_legacy_ctls) {
> > +		/* each hw_intf needs its own hw_ctrl to program its control path */
> > +		num_ctls = top->num_intf;
> >  
> > -	needs_split_display = _dpu_rm_needs_split_display(top);
> > +		needs_split_display = _dpu_rm_needs_split_display(top);
> > +	} else {
> > +		/* use single CTL */
> > +		num_ctls = 1;
> > +		needs_split_display = false;
> > +	}
> >  
> >  	for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
> >  		const struct dpu_hw_ctl *ctl;
> > @@ -402,7 +410,8 @@ static int _dpu_rm_reserve_ctls(
> >  
> >  		DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
> >  
> > -		if (needs_split_display != has_split_display)
> > +		if (rm->has_legacy_ctls &&
> > +		    needs_split_display != has_split_display)
> 
> I deduced a long time ago that the check for rm->has_legacy_ctls is not needed.
> 
> needs_split_display is always false on DPU >= 5, and neither of those SoCs has
> DPU_CTRL_SPLIT_DISPLAY which means false != false is false, and this condition
> never triggers on active CTLs even without checking has_legacy_ctls.

During the transition time of 1 or 2 patches there is a window of
DPU >= 5 and DPU_CTRL_SPLIT_DISPLAY.

> 
> Other than that, this is all successfully tested and:
> 
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> 
> >  			continue;
> >  
> >  		ctl_idx[i] = j;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > index 99bd594ee0d1995eca5a1f661b15e24fdf6acf39..130f753c36338544e84a305b266c3b47fa028d84 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > @@ -24,6 +24,7 @@ struct dpu_global_state;
> >   * @dspp_blks: array of dspp hardware resources
> >   * @hw_sspp: array of sspp hardware resources
> >   * @cdm_blk: cdm hardware resource
> > + * @has_legacy_ctls: DPU uses pre-ACTIVE CTL blocks.
> >   */
> >  struct dpu_rm {
> >  	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
> > @@ -37,6 +38,7 @@ struct dpu_rm {
> >  	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
> >  	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
> >  	struct dpu_hw_blk *cdm_blk;
> > +	bool has_legacy_ctls;
> >  };
> >  
> >  struct dpu_rm_sspp_requirements {
> > 
> > -- 
> > 2.39.5
> >
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5baf9df702b84b74ba00e703ad3cc12afb0e94a4..4dbc9bc7eb4f151f83055220665ee5fd238ae7ba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -53,6 +53,8 @@  int dpu_rm_init(struct drm_device *dev,
 	/* Clear, setup lists */
 	memset(rm, 0, sizeof(*rm));
 
+	rm->has_legacy_ctls = (cat->mdss_ver->core_major_ver < 5);
+
 	/* Interrogate HW catalog and create tracking items for hw blocks */
 	for (i = 0; i < cat->mixer_count; i++) {
 		struct dpu_hw_mixer *hw;
@@ -381,10 +383,16 @@  static int _dpu_rm_reserve_ctls(
 	int i = 0, j, num_ctls;
 	bool needs_split_display;
 
-	/* each hw_intf needs its own hw_ctrl to program its control path */
-	num_ctls = top->num_intf;
+	if (rm->has_legacy_ctls) {
+		/* each hw_intf needs its own hw_ctrl to program its control path */
+		num_ctls = top->num_intf;
 
-	needs_split_display = _dpu_rm_needs_split_display(top);
+		needs_split_display = _dpu_rm_needs_split_display(top);
+	} else {
+		/* use single CTL */
+		num_ctls = 1;
+		needs_split_display = false;
+	}
 
 	for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
 		const struct dpu_hw_ctl *ctl;
@@ -402,7 +410,8 @@  static int _dpu_rm_reserve_ctls(
 
 		DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
 
-		if (needs_split_display != has_split_display)
+		if (rm->has_legacy_ctls &&
+		    needs_split_display != has_split_display)
 			continue;
 
 		ctl_idx[i] = j;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 99bd594ee0d1995eca5a1f661b15e24fdf6acf39..130f753c36338544e84a305b266c3b47fa028d84 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,6 +24,7 @@  struct dpu_global_state;
  * @dspp_blks: array of dspp hardware resources
  * @hw_sspp: array of sspp hardware resources
  * @cdm_blk: cdm hardware resource
+ * @has_legacy_ctls: DPU uses pre-ACTIVE CTL blocks.
  */
 struct dpu_rm {
 	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
@@ -37,6 +38,7 @@  struct dpu_rm {
 	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
 	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
 	struct dpu_hw_blk *cdm_blk;
+	bool has_legacy_ctls;
 };
 
 struct dpu_rm_sspp_requirements {