| Message ID | 20250220-fd-mdp4-lvds-v2-7-15afe5578a31@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/mdp4: rework LVDS/LCDC panel support | expand |
On 20.02.2025 12:14 PM, Dmitry Baryshkov wrote: > Link LVDS clocks to the from MDP4 to the MMCC and back from the MMCC > to the MDP4 display controller. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5f1a6b4b764492486df1a2610979f56c0a37b64a..b884900716464b6291869ff50825762a55099982 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -737,7 +737,8 @@ mmcc: clock-controller@4000000 { <&dsi0_phy 0>, <&dsi1_phy 1>, <&dsi1_phy 0>, - <&hdmi_phy>; + <&hdmi_phy>, + <&mdp>; clock-names = "pxo", "pll3", "pll8_vote", @@ -745,7 +746,8 @@ mmcc: clock-controller@4000000 { "dsi1pllbyte", "dsi2pll", "dsi2pllbyte", - "hdmipll"; + "hdmipll", + "lvdspll"; }; l2cc: clock-controller@2011000 { @@ -1404,13 +1406,19 @@ mdp: display-controller@5100000 { <&mmcc MDP_AXI_CLK>, <&mmcc MDP_LUT_CLK>, <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; + <&mmcc MDP_TV_CLK>, + <&mmcc LVDS_CLK>, + <&rpmcc RPM_PXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_clk", "lut_clk", "hdmi_clk", - "tv_clk"; + "tv_clk", + "lcdc_clk", + "pxo"; + + #clock-cells = <0>; iommus = <&mdp_port0 0 &mdp_port0 2
Link LVDS clocks to the from MDP4 to the MMCC and back from the MMCC to the MDP4 display controller. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)