From patchwork Sun Feb 23 09:31:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13986894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 219CFC021B2 for ; Sun, 23 Feb 2025 09:35:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91BDA10E291; Sun, 23 Feb 2025 09:35:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="UigDPKjj"; dkim-atps=neutral Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id C310810E03A for ; Sun, 23 Feb 2025 09:32:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1740303156; bh=MLcedUWBkgkxVWzbTDCOp0QOw7S68POvgln+Xwcmv1I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UigDPKjjSCsGM11E12jNEGQr7R6tDTTL0aWHv0IB1EZBx8otuJF5l33tmm5BIqRds mNFzcC7xt+NGNy3c565RSYbyeL4xkqO40mBBRvZyUdl+98DNWzIxEqK4MKlDnX/Rp6 qoFrQWg+8hJbsBEzSzTseIEnIjmiz6RbM+5TVW8k9oD5WLiOg5w7G+Orbmp8r9XlBP m58s1WKpNDN4v5MOTQLRBDxqEe6mfU5SCeWzx38nRDtjXrbKA4QyUd5ZgcBxPhmYpe L0HV4IPDYkw3i22wTTB0AcJFxS4mBZRx7jzBLNmIIBjXgtJ/JBmM9M9XLljelGeUv0 K/g9Oh9wG25Zg== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6381117E0CD2; Sun, 23 Feb 2025 10:32:36 +0100 (CET) From: Cristian Ciocaltea Date: Sun, 23 Feb 2025 11:31:39 +0200 Subject: [PATCH v2 3/5] arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 MIME-Version: 1.0 Message-Id: <20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com> References: <20250223-vop2-hdmi1-disp-modes-v2-0-f4cec5e06fbe@collabora.com> In-Reply-To: <20250223-vop2-hdmi1-disp-modes-v2-0-f4cec5e06fbe@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 9bc5287bb6469138c2d9e2fcfec7984c830c2ce5..97e55990e0524ed447d182cef416190822bf67be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -479,6 +479,7 @@ hdptxphy1: phy@fed70000 { reg = <0x0 0xfed70000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,