| Message ID | 20250228-a623-gpu-support-v2-3-aea654ecc1d3@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support for Adreno 623 GPU | expand |
On 27.02.2025 9:07 PM, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add support for Adreno 623 GPU found in QCS8300 chipsets. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index edffb7737a97b268bb2986d557969e651988a344..53e2ff4406d8f0afe474aaafbf0e459ef8f4577d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { > { 0, 0 }, > { 137, 1 }, > ), > + }, { > + .chip_ids = ADRENO_CHIP_IDS(0x06020300), > + .family = ADRENO_6XX_GEN3, > + .fw = { > + [ADRENO_FW_SQE] = "a650_sqe.fw", > + [ADRENO_FW_GMU] = "a623_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > + ADRENO_QUIRK_HAS_HW_APRIV, > + .init = a6xx_gpu_init, > + .a6xx = &(const struct a6xx_info) { > + .hwcg = a690_hwcg, You used the a620 table before, I'm assuming a690 is correct after all? Konrad
On 2/28/2025 1:59 AM, Konrad Dybcio wrote: > On 27.02.2025 9:07 PM, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add support for Adreno 623 GPU found in QCS8300 chipsets. >> >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >> 4 files changed, 43 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> index edffb7737a97b268bb2986d557969e651988a344..53e2ff4406d8f0afe474aaafbf0e459ef8f4577d 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { >> { 0, 0 }, >> { 137, 1 }, >> ), >> + }, { >> + .chip_ids = ADRENO_CHIP_IDS(0x06020300), >> + .family = ADRENO_6XX_GEN3, >> + .fw = { >> + [ADRENO_FW_SQE] = "a650_sqe.fw", >> + [ADRENO_FW_GMU] = "a623_gmu.bin", >> + }, >> + .gmem = SZ_512K, >> + .inactive_period = DRM_MSM_INACTIVE_PERIOD, >> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | >> + ADRENO_QUIRK_HAS_HW_APRIV, >> + .init = a6xx_gpu_init, >> + .a6xx = &(const struct a6xx_info) { >> + .hwcg = a690_hwcg, > > You used the a620 table before, I'm assuming a690 is correct after all? Correct. a690_hwcg array has the recommended values for a623. -Akhil. > > Konrad
On 27.02.2025 10:06 PM, Akhil P Oommen wrote: > On 2/28/2025 1:59 AM, Konrad Dybcio wrote: >> On 27.02.2025 9:07 PM, Akhil P Oommen wrote: >>> From: Jie Zhang <quic_jiezh@quicinc.com> >>> >>> Add support for Adreno 623 GPU found in QCS8300 chipsets. >>> >>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ >>> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- >>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >>> 4 files changed, 43 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index edffb7737a97b268bb2986d557969e651988a344..53e2ff4406d8f0afe474aaafbf0e459ef8f4577d 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { >>> { 0, 0 }, >>> { 137, 1 }, >>> ), >>> + }, { >>> + .chip_ids = ADRENO_CHIP_IDS(0x06020300), >>> + .family = ADRENO_6XX_GEN3, >>> + .fw = { >>> + [ADRENO_FW_SQE] = "a650_sqe.fw", >>> + [ADRENO_FW_GMU] = "a623_gmu.bin", >>> + }, >>> + .gmem = SZ_512K, >>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD, >>> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | >>> + ADRENO_QUIRK_HAS_HW_APRIV, >>> + .init = a6xx_gpu_init, >>> + .a6xx = &(const struct a6xx_info) { >>> + .hwcg = a690_hwcg, >> >> You used the a620 table before, I'm assuming a690 is correct after all? > > Correct. a690_hwcg array has the recommended values for a623. Thanks for double checking Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add support for Adreno 623 GPU found in QCS8300 chipsets. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 0ae29a7c8a4d3f74236a35cc919f69d5c0a384a0..1820c167fcee609deee3d49e7b5dd3736da23d99 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > gpu->ubwc_config.uavflagprd_inv = 2; > } > > + if (adreno_is_a623(gpu)) { > + gpu->ubwc_config.highest_bank_bit = 16; Just to doublecheck, the MDSS patch for QCS8300 used HBB=2, which means 15. Is 16 correct here? Or might the be a mistake in the MDSS patch? > + gpu->ubwc_config.amsbc = 1; > + gpu->ubwc_config.rgb565_predicator = 1; > + gpu->ubwc_config.uavflagprd_inv = 2; > + gpu->ubwc_config.macrotile_mode = 1; > + } > + > if (adreno_is_a640_family(gpu)) > gpu->ubwc_config.amsbc = 1; >
On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote: > On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add support for Adreno 623 GPU found in QCS8300 chipsets. >> >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >> 4 files changed, 43 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 0ae29a7c8a4d3f74236a35cc919f69d5c0a384a0..1820c167fcee609deee3d49e7b5dd3736da23d99 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) >> gpu->ubwc_config.uavflagprd_inv = 2; >> } >> >> + if (adreno_is_a623(gpu)) { >> + gpu->ubwc_config.highest_bank_bit = 16; > > Just to doublecheck, the MDSS patch for QCS8300 used HBB=2, which > means 15. Is 16 correct here? Or might the be a mistake in the MDSS > patch? https://patchwork.freedesktop.org/patch/632957/ I see HBB=3 here. -Akhil > >> + gpu->ubwc_config.amsbc = 1; >> + gpu->ubwc_config.rgb565_predicator = 1; >> + gpu->ubwc_config.uavflagprd_inv = 2; >> + gpu->ubwc_config.macrotile_mode = 1; >> + } >> + >> if (adreno_is_a640_family(gpu)) >> gpu->ubwc_config.amsbc = 1; >>
On Fri, Feb 28, 2025 at 01:43:12PM +0530, Akhil P Oommen wrote: > On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote: > > On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote: > >> From: Jie Zhang <quic_jiezh@quicinc.com> > >> > >> Add support for Adreno 623 GPU found in QCS8300 chipsets. > >> > >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > >> --- > >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++ > >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ > >> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- > >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > >> 4 files changed, 43 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> index 0ae29a7c8a4d3f74236a35cc919f69d5c0a384a0..1820c167fcee609deee3d49e7b5dd3736da23d99 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > >> @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) > >> gpu->ubwc_config.uavflagprd_inv = 2; > >> } > >> > >> + if (adreno_is_a623(gpu)) { > >> + gpu->ubwc_config.highest_bank_bit = 16; > > > > Just to doublecheck, the MDSS patch for QCS8300 used HBB=2, which > > means 15. Is 16 correct here? Or might the be a mistake in the MDSS > > patch? > > https://patchwork.freedesktop.org/patch/632957/ > I see HBB=3 here. Indeed. Excuse me for the noise. > > -Akhil > > > > >> + gpu->ubwc_config.amsbc = 1; > >> + gpu->ubwc_config.rgb565_predicator = 1; > >> + gpu->ubwc_config.uavflagprd_inv = 2; > >> + gpu->ubwc_config.macrotile_mode = 1; > >> + } > >> + > >> if (adreno_is_a640_family(gpu)) > >> gpu->ubwc_config.amsbc = 1; > >> >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index edffb7737a97b268bb2986d557969e651988a344..53e2ff4406d8f0afe474aaafbf0e459ef8f4577d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = { { 0, 0 }, { 137, 1 }, ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06020300), + .family = ADRENO_6XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "a650_sqe.fw", + [ADRENO_FW_GMU] = "a623_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .a6xx = &(const struct a6xx_info) { + .hwcg = a690_hwcg, + .protect = &a650_protect, + .gmu_cgc_mode = 0x00020200, + .prim_fifo_threshold = 0x00010000, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + }, + { /* sentinel */ }, + }, + }, + .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS( 0x06030001, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0ae29a7c8a4d3f74236a35cc919f69d5c0a384a0..1820c167fcee609deee3d49e7b5dd3736da23d99 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.uavflagprd_inv = 2; } + if (adreno_is_a623(gpu)) { + gpu->ubwc_config.highest_bank_bit = 16; + gpu->ubwc_config.amsbc = 1; + gpu->ubwc_config.rgb565_predicator = 1; + gpu->ubwc_config.uavflagprd_inv = 2; + gpu->ubwc_config.macrotile_mode = 1; + } + if (adreno_is_a640_family(gpu)) gpu->ubwc_config.amsbc = 1; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 2c10474ccc95cf2515c6583007a9b5cc478f836c..3222a406d08950008ca8c67a9b78cdd0e98e888c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1227,7 +1227,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], &a6xx_state->gmu_registers[1], true); - if (adreno_is_a621(adreno_gpu)) + if (adreno_is_a621(adreno_gpu) || adreno_is_a623(adreno_gpu)) _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg, &a6xx_state->gmu_registers[2], false); else diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index dcf454629ce037b2a8274a6699674ad754ce1f07..92caba3584da0400b44a903e465814af165d40a3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -442,6 +442,11 @@ static inline int adreno_is_a621(const struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x06020100; } +static inline int adreno_is_a623(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x06020300; +} + static inline int adreno_is_a630(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 630);